Specifications | PI6C48533-01.indd jtho |
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Specifications | PI6C48533-01.indd jtho |
Business section |
Specifications | PI6C48533-01.indd jtho |
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Content | 1PS8737B 12/15/09 PI6C48533-01 Block Diagram Features • Pin-to-pin compatible to ICS8533-01 • Maximum operation frequency: 800MHz • 4 pair of differential LVPECL outputs • Selectable differential CLK and PCLK inputs • CLK, nCLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and HCSL input level • PCLK, nPCLK pair supports LVPECL, CML and SSTL input level • Output Skew: 100ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagation delay: 2ns (maximum) • 3.3V power supply • Operating Temperature: -40oC to 85oC • Packaging (Pb-free & Green avaliable): -20-pin TSSOP (L) 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Description The PI6C48533-01 is a high-performance low-skew LVPECL fanout buffer. PI6C48533-01 features two selectable differential inputs and translates to four LVPECL ultra-low jitter outputs. The inputs can also be confi gured to single-ended with external resistor bias circuit. The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL or CML signals. The outputs are synchronized with input clock during asyn- chronous assertion/deassertion of CLK_EN pin. PI6C48533-01 is ideal for differential to LVPECL translations and/or LVPECL clock distribution. Typical clock translation and distribution applications are data-communications and telecommunications. Pin Diagram CLK_EN CLK nCLK PCLK nPCLK CLK_SEL Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 0 1 D LE Q Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK NC NC VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 09-0110 |
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Following Datasheets | PI6C48535-01_2 (5 pages) PI6C49003_2 (12 pages) PI6C49004_2 (12 pages) PI6C557-03_2 (8 pages) PI6C557-03A_2 (9 pages) PI6C557-03B_3 (9 pages) PI6C557-05_3 (9 pages) PI6C557-05B_3 (8 pages) PI6C557-10_3 (6 pages) PI6CL10804_2 (6 pages) |
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