3.14_GAL20XV10 3.14_GAL20XV10 coughlin

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Specifications	3.14_GAL20XV10 3.14_GAL20XV10 coughlin
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GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic™ 1 228 NC I/CLK I I I I I I I I NCNC NC GND I I I/O/Q I/O/Q I/O/Q I

Specifications	3.14_GAL20XV10 3.14_GAL20XV10 coughlin
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Content	GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic™ 1 228 NC I/CLK I I I I I I I I NCNC NC GND I I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I/O/Q I/O/Q I/O/Q I/OE 4 5 7 9 11 12141618 19 21 23 25 26 1 1213 24I/CLK I I I I I I I I I I GND Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/OE 6 18 Description The GAL20XV10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed Exclusive-OR PLD available in the market. At 90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides a substantial savings in power when compared to bipolar counter- parts. E2CMOS technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the de- vices quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configu- rations possible with the GAL20XV10 are the PAL® architectures listed in the macrocell description section of this document. The GAL20XV10 is capable of emulating these PAL architectures with full function and parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. GAL20XV10 Top View PLCC DIP Features •HIGH PERFORMANCE E2CMOS ® TECHNOLOGY—10 ns Maximum Propagation Delay—Fmax = 100 MHz—7 ns Maximum from Clock Input to Data Output—TTL Compatible 16 mA Outputs—UltraMOS® Advanced CMOS Technology •50% to 75% REDUCTION IN POWER FROM BIPOLAR—90mA Maximum Icc—75mA Typical Icc •ACTIVE PULL-UPS ON ALL PINS •E2 CELL TECHNOLOGY—Reconfigurable Logic—Reprogrammable Cells—100% Tested/100% Yields—High Speed Electrical Erasure (<100 ms)—20 Year Data Retention •TEN OUTPUT LOGIC MACROCELLS— XOR Gate Capability on all Outputs—Full Function and Parametric Compatibility withPAL12L10, 20L10, 20X10, 20X8, 20X4—Registered or Combinatorial with Polarity •PRELOAD AND POWER-ON RESET OF ALL REGISTERS •APPLICATIONS INCLUDE:—High Speed Counters—Graphics Processing— Comparators •ELECTRONIC SIGNATURE FOR IDENTIFICATION GAL 20XV10 PROGRAMMABLE AND-ARRAY (40 X 40) I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/CLK I I I I I I I I I I4 4 4 4 4 4 4 4 4 4 OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC I/OE Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.July 1997 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 20xv10_02 Functional Block Diagram Pin Configuration Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
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Following Datasheets	20_ASB_2011_MRO_Training_Section782299-1 (1 pages) 20_coc2008Chinese_Traditional (22 pages) 20_oita_20120118 (4 pages) 20_pdip_d_customer_format (1 pages) 20_pdip_pb-free (1 pages) 20_plcc (1 pages) 20_plcc_pb-free (1 pages) 21-1_1 (2 pages) 21-2 (1 pages) 211_1 (2 pages)
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