3.13_GAL20VP8 3.13_GAL20VP8 coughlin

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Specifications	3.13_GAL20VP8 3.13_GAL20VP8 coughlin
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GAL20VP8 High-Speed E2CMOS PLD Generic Array Logic™ 1 Features •HIGH DRIVE E2CMOS® GAL® DEVICE —T

Specifications	3.13_GAL20VP8 3.13_GAL20VP8 coughlin
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Content	GAL20VP8 High-Speed E2CMOS PLD Generic Array Logic™ 1 Features •HIGH DRIVE E2CMOS® GAL® DEVICE —TTL Compatible 64 mA Output Drive —15 ns Maximum Propagation Delay —Fmax = 80 MHz —10 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •ENHANCED INPUT AND OUTPUT FEATURES —Schmitt Trigger Inputs —Programmable Open-Drain or Totem-Pole Outputs —Active Pull-Ups on All Inputs and I/O pins •E2 CELL TECHNOLOGY —Reconfigurable Logic —Reprogrammable Cells —100% Tested/100% Yields —High Speed Electrical Erasure (<100ms) —20 Year Data Retention •EIGHT OUTPUT LOGIC MACROCELLS —Maximum Flexibility for Complex Logic Designs —Programmable Output Polarity —Architecturally Compatible with Standard GAL20V8 •PRELOAD AND POWER-ON RESET OF ALL REGISTERS —100% Functional Testability •APPLICATIONS INCLUDE: —Ideal for Bus Control & Bus Arbitration Logic —Bus Address Decode Logic —Memory Address, Data and Control Circuits —DMA Control •ELECTRONIC SIGNATURE FOR IDENTIFICATION 1 1213 24I/CLK I I I I I I I I I I GND Vcc I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q II/OE 6 18 228 NC I/CLK I I I I I I NCNC NC I I I/OE I/O/Q I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q I/O/Q Vcc I/O/Q I I I I 426 5 7 9 11 1214161819 21 23 25 GAL20VP8 Top View DIPPLCC GAL 20VP8 I I I I I I I I I CLK I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I I/OE I/CLK OE 8 8 8 8 8 8 8 8 OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC IMUX IMUX PROGRAMMABLE AND-ARRAY (64 X 40) I Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.December 1997 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 20vp8_03 Description The GAL20VP8, with 64 mA drive capability and 15ns maximum propagation delay time is ideal for Bus and Memory control appli- cations. The GAL20VP8 is manufactured using Lattice Semiconductor s advanced E2CMOS process which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. System bus and memory interfaces require control logic before driving the bus or memory interface signals. The GAL20VP8 combines the familiar GAL20V8 architecture with bus drivers as its outputs. The generic architecture provides maximum design flex- ibility by allowing the Output Logic Macrocell (OLMC) to be con- figured by the user. The 64mA output drive eliminates the need for additional devices to provide bus-driving capability. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Functional Block Diagram Pin Configuration Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
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