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| Content | Evaluation of Power MOSFET Thermal Solutions for Desktop and Mobile Processor Power Tim McDonald and John Ambrus International Rectifier Corporation 233 Kansas Street El Segundo, CA 90245 USA Tmcdona1@irf.com, jambrus1@irf.com as presented at PCIM China, March 2002 Abstract This paper surveys the thermal performance capabilities of various power semiconductor package types available to the designer of surface mounted motherboard and/or mobile processor power systems. The packages studied are mostly variants of the SO-8 type footprint and include standard SO-8, several improved thermal SO-8 types, D-Pak and D2Pak footprint packages and the DirectFETTM MOSFET. Steady state thermal Resistance is measured and the effects of heatsinking, PCB layout/area, and airflow are all considered. It is seen that the DirectFETTM MOSFET packaging technology allows for dramatically cooler operation or much higher output power in a given footprint, especially when two sided cooling is allowed. Introduction The desktop or mobile computer system designer is challenged today to provide appropriate power to latest microprocessors. With each successive generation operating frequency, performance, and integration level have gone up, increasing power dissipation. At the same time operating voltage has gone down thus driving up the current needed for given power level. As performance/frequency have increased, the required slew rates go up1. At the power switch packaging level, these demands add up to requirements of higher power dissipation and lower parasitics. Power Packaging Solutions Historically, traditional SOIC packages such as SO-8 (see figure 1) have been adapted to power semiconductor use in microprocessor voltage regulation. As one might expect from a package not designed to the purpose, serious performance limitations result. Standard construction SO-8 thermal performance is limited by heat dissipation through the leads and onto the PCB2. Stray package resistance and inductance likewise suffer from the wirebond and lead construction. More recently several “improved thermal” variants of SO-8 have been introduced by multiple suppliers. These packages include Copper strap SO-83 (see figures 2-3) wherein the lead and wirebond construction are replaced by a solder and Copper strap assembly (reduces Rds-on and improves thermal resistance), and MLP or “leadless SO-8” types (new JEDEC MO220 designation, see figure 4) which have exposed Cu die mounting pad (reduces Rth) and Cu lead pads molded into the epoxy body coplanar with the die mounting pad. Yet another package option is the D-pak (see figure 5). Compared to SO-8 types, and thanks to a Silicon die to Copper tab to PCB design, both D-Pak and MLP/Leadless thermal resistance junction to case/lead is improved. But as with SO-8, wirebond and lead construction still results in higher than desired package stray resistance. For all types so far mentioned, Power dissipation is limited by the ability to dissipate heat from the Silicon junction through packaging material to the PCB and then from the PCB to ambient. For the most thermally efficient packages listed, the D-Pak and MLP, the Rth contribution from Junction through packaging materials is quite low but the power dissipation is still very constrained by RTH between lead to PCB to ambient. It is clear that if further power is to be dissipated from the same form factor, then it must seek another path. Figure 1: SO-8 |
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| Following Datasheets | Thermal_Cross_Ref (2 pages) Thermal_Imped (3 pages) Thermal_Mgmnt_Products-1 (20 pages) thermal_overload_relays (8 pages) Thermal_Products_Brochure (4 pages) Thermax_ISO_cert (1 pages) thermele (6 pages) thermistoraging (4 pages) thermistorcurves (4 pages) thermistordissipation (4 pages) |
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