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Specifications

This chapter describes how Arria II devices provide I/O capabilities that allow you to work in compli\ ance with current and emerging I/O standards and requirements. I/O Features in Arria II Devices - Arria II Device Handbook, Volume 1, Chapter 6 Arria II GX, Arria II GZ, I/O standards, voltage levels, I/O banks, I/O structure, OCT support, OCT c\ alibration, termination schemes, design considerations Altera Corporation

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6–4Chapter 6:I/O Features in Arria II Devices I/O Standards Support Arria II Device Handbook Volume 1: Device Interface

Specifications	This chapter describes how Arria II devices provide I/O capabilities that allow you to work in compli\ ance with current and emerging I/O standards and requirements. I/O Features in Arria II Devices - Arria II Device Handbook, Volume 1, Chapter 6 Arria II GX, Arria II GZ, I/O standards, voltage levels, I/O banks, I/O structure, OCT support, OCT c\ alibration, termination schemes, design considerations Altera Corporation
Outline	6. I/O Features in Arria II Devices I/O Standards Support I/O Banks Modular I/O Banks I/O Structure 3.3-V I/O Interface External Memory Interfaces High-Speed Differential I/O with DPA Support Programmable Current Strength Programmable Slew Rate Control Open-Drain Output Bus Hold Programmable Pull-Up Resistor Programmable Pre-Emphasis Programmable Differential Output Voltage MultiVolt I/O Interface
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Content	6–4Chapter 6:I/O Features in Arria II Devices I/O Standards Support Arria II Device Handbook Volume 1: Device Interfaces and IntegrationDecember 2011Altera Corporation fFor detailed electrical characteristics of each I/O standard, refer to the Device Datasheet for ArriaII Devices. LVDS (4), (5), (8)ANSI/TIA/ EIA-644(2)(2)2.52.52.5—— RSDS (6), (7), (8)—(2)(2)2.52.52.5—— mini-LVDS (6), (7), (8)—(2)(2)2.52.52.5—— LVPECL—(4)2.5——2.5—— Notes to Table6–2: (1)VCCPD is either 2.5 or 3.0V. For VCCIO = 3.0 V, VCCPD = 3.0 V. For VCCIO = 2.5 V or less, VCCPD = 2.5 V. (2)Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by VCCPD. Row I/O banks support both true differential input buffers and true differential output buffers. Column I/O banks support true differential input buffers, but not true differential output buffers. I/O pins are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without RD OCT support. (3)For more information about the 3.3-V LVTTL/LVCMOS standard supported in Arria II devices, refer to “3.3-V I/O Interface” on page6–13. (4)Column I/O banks support LVPECL I/O standards for input clock operation. Clock inputs on column I/Os are powered by VCCCLKIN when configured as differential clock inputs. They are powered by VCCIO when configured as single-ended clock inputs. Differential clock inputs in row I/Os are powered by VCCPD. (5)Column and row I/O banks support LVDS outputs using two single-ended output buffers, an external one-resistor (LVDS_E_1R), and a three-resistor (LVDS_E_3R) network. (6)Row I/O banks support RSDS and mini-LVDS I/O standards using a true LVDS output buffer without a resistor network. (7)Column and row I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with one-resistor (RSDS_E_1R and mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks. (8)The emulated differential output standard that supports the tri-state feature includes: LVDS_E_1R, LVDS_E_3R, RSDS_E_1R, RSDS_E_3R, Mini_LVDS_E_1R, and Mini_LVDS_E_3R. For more information, refer to the I/O Buffer (ALTIOBUF) Megafunction User Guide. Table6–2.I/O Standards and Voltage Levels for Arria II GZ Devices(Note1)(Part 2 of 2) I/O StandardStandard Support VCCIO (V) VCCPD (V) (Pre- Driver Voltage) VREF (V) (Input Ref Voltage) VTT (V) (Board Termination Voltage) Input OperationOutput Operation Column I/O Banks Row I/O Banks Column I/O Banks Row I/O Banks
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