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| Specifications | describes all the modules that are available in the Arria II GX and GZ transceiver architecture and i\ llustrates how these modules are used in the protocols shown below. Transceiver Architecture for Arria II Devices, Arria II Device Handbook, Volume 2 transceiver architecture, CMU channel, CMU0, CMU1, transmitter channel, receiver channel, functional \ modes, calibration blocks, Arria II GX, Arria II GZ, PCIe, PCIe hard IP Altera Corporation |
| Business section |
| Specifications | describes all the modules that are available in the Arria II GX and GZ transceiver architecture and i\ llustrates how these modules are used in the protocols shown below. Transceiver Architecture for Arria II Devices, Arria II Device Handbook, Volume 2 transceiver architecture, CMU channel, CMU0, CMU1, transmitter channel, receiver channel, functional \ modes, calibration blocks, Arria II GX, Arria II GZ, PCIe, PCIe hard IP Altera Corporation |
| Outline | 1. Transceiver Architecture in Arria II Devices Transceiver Block Overview Clock Multiplier Units (CMU) CMU PLL CMU0 Clock Divider Transceiver Channel Architecture Transmitter Channel Datapath Transmitter PCS TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Calibration Block PCIe Hard IP Block Functional Modes Test Modes Dynamic Reconfiguration Transceiver Port List Document Revision History |
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| Content | Arria II Device Handbook Volume 2: Transceivers December 2011 AIIGX52001-4.2 Subscribe © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 1.Transceiver Architecture in Arria II Devices This chapter describes all available modules in the Arria® II GX and GZ transceiver architecture and describes how these modules are used in the protocols shown in Table1–1. In addition, this chapter lists the available test modes, dynamic reconfiguration, and ALTGX port names. Arria II GX and GZ devices provide up to 24 full-duplex clock data recovery-based (CDR) transceivers with physical coding sublayer (PCS) and physical medium attachment (PMA), and support the serial protocols listed in Table1–1 and Table1–2. Table1–1 lists the serial protocols for Arria II GX devices. Table1–1.Serial Protocols for Arria II GX Devices ProtocolDescription PCI Express® (PIPE) (PCIe®)Gen1, 2.5 Gbps Serial RapidIO® (SRIO)1.25 Gbps, 2.5 Gbps, and 3.125 Gbps Serial ATA (SATA)/ Serial Attached SCSI (SAS) ■SATA I, 1.5 Gbps ■SATA II, 3.0 Gbps ■SATA III, 6.0 Gbps ■SAS, 1.5 Gbps and 3.0 Gbps Serial Digital Interface (SDI) ■HD-SDI, 1.485 Gbps and 1.4835 Gbps ■3G-SDI, 2.97 Gbps and 2.967 Gbps ASI270 Mbps Common Public Radio Interface (CPRI) 614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps, 3072 Mbps, 4915.2Mbps, and 6144 Mbps OBSAI768 Mbps, 1536 Mbps, 3072 Mbps, and 6144 Mbps Gigabit Ethernet (GbE)1.25 Gbps XAUI3.125 Gbps to 3.75 Gbps for HiGig/HiGig+ support SONET/SDH ■OC-3 (155 Mbps) ■OC-12 (622 Mbps) ■OC-48 (2.488 Gbps) GPON1.244 uplink and 2.488 downlink SerialLite II0.6 Gbps to 3.75 Gbps Interlaken— CEI— December 2011 AIIGX52001-4.2 |
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| Following Datasheets | aiigx_53001 (78 pages) aiigx_5v1 (380 pages) aiigx_5v2 (222 pages) aiigx_5v3_1 (90 pages) Air_Glass (5 pages) air-condition_system-1 (3 pages) air-condition_system (3 pages) Aircraft_Interiors_Anwendungen (2 pages) Aircraft_Interiors_Flyer (2 pages) Airforce_bro_de-2 (11 pages) |
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