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| Specifications | This chapter describes how Arria II devices provide I/O capabilities that allow you to work in compli\ ance with current and emerging I/O standards and requirements. I/O Features in Arria II Devices - Arria II Device Handbook, Volume 1, Chapter 6 Arria II GX, Arria II GZ, I/O standards, voltage levels, I/O banks, I/O structure, OCT support, OCT c\ alibration, termination schemes, design considerations Altera Corporation |
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| Specifications | This chapter describes how Arria II devices provide I/O capabilities that allow you to work in compli\ ance with current and emerging I/O standards and requirements. I/O Features in Arria II Devices - Arria II Device Handbook, Volume 1, Chapter 6 Arria II GX, Arria II GZ, I/O standards, voltage levels, I/O banks, I/O structure, OCT support, OCT c\ alibration, termination schemes, design considerations Altera Corporation |
| Outline | 6. I/O Features in Arria II Devices I/O Standards Support I/O Banks Modular I/O Banks I/O Structure 3.3-V I/O Interface External Memory Interfaces High-Speed Differential I/O with DPA Support Programmable Current Strength Programmable Slew Rate Control Open-Drain Output Bus Hold Programmable Pull-Up Resistor Programmable Pre-Emphasis Programmable Differential Output Voltage MultiVolt I/O Interface |
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| Content | Chapter 6:I/O Features in Arria II Devices6–33 Termination Schemes for I/O Standards December 2011Altera CorporationArria II Device Handbook Volume 1: Device Interfaces and Integration Differential LVPECL Arria II devices support the LVPECL I/O standard on input clock pins only. LVPECL output operation is not supported. LVDS input buffers are used to support LVPECL input operation. AC-coupling is required when the LVPECL common mode voltage of the output buffer is higher than Arria II LVPECL input common mode voltage. Figure6–16 shows the AC-coupled termination scheme. The 50-: resistors used at the receiver end are external to the device. Arria II devices support DC-coupled LVPECL if the LVPECL output common mode voltage is within the Arria II LVPECL input buffer specification (Figure6–17). RSDS Arria II devices supports true RSDS, RSDS with a one-resistor network, and RSDS with a three-resistor network. Two single-ended output buffers are used for external one- or three-resistor networks, as shown in Figure6–18. Only Arria II GZ row I/O banks support RSDS output using true LVDS output buffers without an external resistor network. Figure6–16.LVPECL AC-Coupled Termination Figure6–17.LVPECL DC-Coupled Termination LVPECL Output Buffer Arria II LVPECL Input Buffer VICM ZO ZO 0.1 µF 0.1 µF LVPECL Output Buffer Arria II LVPECL Input Buffer 100 Ω = 50 ΩZO = 50 ΩZO |
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