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Rev. E | Page 51 of 108 LLC1SFL P19 TOP10ADV7403VIDEODECODER CLKIN SFL PIXEL PORT5 RTC LOW 128 TIME SLOT 01 130 14 21 19 FSC

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Content	Rev. E \| Page 51 of 108 LLC1SFL P19 TOP10ADV7403VIDEODECODER CLKIN SFL PIXEL PORT5 RTC LOW 128 TIME SLOT 01 130 14 21 19 FSC PLL INCREMENT2 VALIDSAMPLEINVALIDSAMPLE 6768 0 RESET BIT4 RESERVED ADV739x 8/LINELOCKEDCLOCK 5 BITSRESERVED 1FOR EXAMPLE, VCR OR CABLE. 2FSCPLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx FSC DDS REGISTER IS FSC PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS. 3SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 4RESET ADV739x DDS. 5REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS. COMPOSITE VIDEO1 H/L TRANSITIONCOUNT START 14 BITSSUBCARRIERPHASE SEQUENCE BIT3 DAC 1 DAC 2 DAC 3 4 BITSRESERVED 06234-064 高清隔行外部HSYNC和VSYNC考虑如果编码器版本代码(子地址0xBB位[7:6])为01或更高，则用户应将子地址0x02位1设为高电平，以确保在高清隔行模式下使用HSYNC和VSYNC同步信号时时序完全正确。如果将此位设为低电平，则在高清隔行模式下，每行的第一个有效像素被屏蔽，并且当使用YCrCb 4:2:2输入格式时，Pr和Pb输出交换。将子地址0x02位1设为低电平时，编码器的工作方式与第一版芯片相同(即此设置为向后兼容设置)。如果编码器版本代码(子地址0xBB位[7:6])为00，则子地址0x02位1的设置不起作用。对于此版本的编码器，当使用YCrCb 4:2:2输入格式时，第一个有效像素被屏蔽， Pr和Pb输出交换。为避免这些限制，请使用新版芯片或使用不同类型的同步。这些考虑因素仅适用于采用外部HSYNC和VSYNC同步的高清隔行模式(EAV/SAV模式不受影响，始终具有完全正确的时序)。将子地址0x02位0设为高电平没有副作用，而且对于所有其它视频标准，此位可保持高电平状态。增清/高清时序复位子地址0x34位0 将增清/高清时序复位控制位(子地址0x34位0)置1时，可实现增清/高清时序复位。在这种状态下，水平和垂直计数器保持复位状态。将此位重新置0时，内部计数器恢复计数。此时序复位仅适用于增清/高清时序计数器。标清副载波频率锁定副载波频率锁定(SFL)模式在副载波频率锁定(SFL)模式下(子地址0x84位[2:1] = 11)， ADV739x可用于锁定外部视频源。SFL模式允许ADV739x 自动变更副载波频率以补偿线长变化。当该器件连接到输出SFL格式数字数据流的器件(如视频解码器ADV7403等) 时，该器件会逐行自动变更为经过补偿的副载波频率(见图 63)。此数字数据流为67位宽，副载波包含于位0至位21 中。每位的时长为2个时钟周期。图63. 标清副载波频率锁定时序和连接图(子地址0x84位[2:1] = 11) ADV7390/ADV7391/ADV7392/ADV7393
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