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| Specifications | Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation |
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| Specifications | Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation |
| Outline | Arria II Device Handbook Volume 2: Transceivers Contents Chapter Revision Dates Section 1. Transceiver Architecture for Arria II Devices Revision History 1. Transceiver Architecture in Arria II Devices Transceiver Block Overview Clock Multiplier Units (CMU) CMU PLL CMU0 Clock Divider Transceiver Channel Architecture Transmitter Channel Datapath Transmitter PCS TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Calibration Block PCIe Hard IP Block Functional Modes Test Modes Dynamic Reconfiguration Transceiver Port List Document Revision History |
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| Content | 1–68Chapter 1:Transceiver Architecture in Arria II Devices Functional Modes Arria II Device Handbook Volume 2: TransceiversDecember 2011Altera Corporation Figure1–65 and Figure1–66 show the receiver detect operation where a receiver was successfully detected and where a receiver was not detected, respectively. Compliance Pattern Transmission Support The LTSSM state machine can enter the polling.compliance substate where the transmitter must transmit a compliance pattern as specified in the PCIe Base Specification 2.0. The polling.compliance substate is intended to assess if the transmitter is electrically compliant with the PCIe voltage and timing specifications. The compliance pattern is a repeating sequence of the following four code groups: ■/K28.5/ ■/D21.5/ ■/K28.5/ ■/D10.2/ The PCIe protocol requires the first /K28.5/ code group of the compliance pattern to be encoded with negative current disparity. To satisfy this requirement, the PIPE interface block provides an input signal (tx_forcedispcompliance). A high level on the tx_forcedispcompliance signal forces the associated parallel transmitter data on the tx_datain port to transmit with a negative current running disparity. 1For 8-bit transceiver channel width configurations, you must drive the tx_forcedispcompliance signal high in the same parallel clock cycle as the first /K28.5/ of the compliance pattern on the tx_datain port. For 16-bit transceiver channel width configurations, you must drive only the LSB of the tx_forcedispcompliance[1:0] signal high in the same parallel clock cycle as /K28.5/D21.5/ of the compliance pattern on the tx_datain port. Figure1–65.Receiver Detect Successful Operation Figure1–66.Receiver Detect Unsuccessful Operation pipephydonestatus pipestatus[2:0]3 b0113 b000 powerdown[1:0] tx_detectrxloopback 2 b10(P1) pipephydonestatus pipestatus[2:0]3 b000 powerdown[1:0] tx_detectrxloopback 2 b10(P1) |
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