Specifications | Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation |
Outline | Arria II Device Handbook Volume 2: Transceivers Contents Chapter Revision Dates Section 1. Transceiver Architecture for Arria II Devices Revision History 1. Transceiver Architecture in Arria II Devices Transceiver Block Overview Clock Multiplier Units (CMU) CMU PLL CMU0 Clock Divider Transceiver Channel Architecture Transmitter Channel Datapath Transmitter PCS TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Calibration Block PCIe Hard IP Block Functional Modes Test Modes Dynamic Reconfiguration Transceiver Port List Document Revision History |
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Content | Chapter 1:Transceiver Architecture in Arria II Devices1–51 Functional Modes December 2011Altera CorporationArria II Device Handbook Volume 2: Transceivers ■XAUI (3.125 Gbps up to HiGig and HiGig+ at 3.75 Gbps) The following sections describe the functional modes available in the ALTGX MegaWizard Plug-In Manager that you can set through the Which protocol will you be using? option. Table1–15 lists the PCS latency for the different functional modes of Arria II devices. Basic Mode The Arria II GX and GZ transceiver datapath is highly flexible in Basic functional mode. It allows 8-bit and 10-bit PMA-to-PCS interface, which is determined by whether you bypass or use the 8B/10B encoder/decoder. Depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks in Basic mode but the transmitter and RX phase compensation FIFOs are always enabled. The word aligner is always enabled in regular Basic mode, but bypassed in low latency PCS mode, which can be enabled through the Enable low latency PCS mode option in the ALTGX MegaWizard Plug-In Manager. The low latency PCS mode creates a Basic functional mode configuration that bypasses the following transmitter and receiver channel PCS blocks to form a low latency PCS datapath: ■8B/10B encoder and decoder ■Word aligner ■Deskew FIFO ■Rate match (clock rate compensation) FIFO ■Byte ordering Table1–15.Functional Modes PCS Latency for Arria II Devices(Note1) Functional Mode PCS Latency (FPGA Fabric-Transceiver Interface Clock Cycles) TX PCSRX PCS Basic(2)(2) Deterministic latency46 (byte SERDES enabled) 8 (byte SERDES disabled) GbE5–620–24 PCIe4–5.5 (byte SERDES enabled) 5–6 (byte SERDES disabled) 11.5–14.5 (byte SERDES enabled) 20–24 (byte SERDES disabled) SDI4–5.5 (byte SERDES enabled) 5–6 (byte SERDES disabled) 6–8 (byte SERDES enabled) 9–11 (byte SERDES disabled) SRIOTBDTBD SONET/SDH5–6 (OC-12)4–5.5 (OC-48)4–5.5 (OC-96)11–13 (OC-12)7–9 (OC-48)6.5–8.5 (OC-96) XAUI4.5–614.5–18 Notes to Table1–15: (1)Not all modes are support by both Arria II GX and Arria II GZ devices. Refer to the respective functional mode sections for the supported modes in each device family. (2)For basic mode latency values, refer to Figure1–51, Figure1–52, Figure1–53, and Figure1–54. |
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