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| Specifications | Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation |
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| Specifications | Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation |
| Outline | Arria II Device Handbook Volume 2: Transceivers Contents Chapter Revision Dates Section 1. Transceiver Architecture for Arria II Devices Revision History 1. Transceiver Architecture in Arria II Devices Transceiver Block Overview Clock Multiplier Units (CMU) CMU PLL CMU0 Clock Divider Transceiver Channel Architecture Transmitter Channel Datapath Transmitter PCS TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Calibration Block PCIe Hard IP Block Functional Modes Test Modes Dynamic Reconfiguration Transceiver Port List Document Revision History |
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| Content | Chapter 4:Reset Control and Power Down in ArriaII Devices4–11 Transceiver Reset Sequences June 2011Altera CorporationArria II Device Handbook Volume 2: Transceivers Transmitter Only Channel This configuration contains only a transmitter channel. If you create a Transmitter Only instance in the ALTGX MegaWizard Plug-In Manager, use the same reset sequence as shown in Figure4–2 on page4–5. Receiver Only Channel—Receiver CDR in Automatic Lock Mode This configuration contains only a receiver channel. If you create a Receiver Only instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in automatic lock mode, use the reset sequence shown in Figure4–6. As shown in Figure4–6, perform the following reset sequence steps for the receiver CDR in automatic lock mode configuration: 1.After power up, wait for the busy signal to be de-asserted (marker 1). 2.De-assert the rx_analogreset signal (marker 2). 3.Keep the rx_digitalreset signal asserted during this time period. After you de-assert the rx_analogreset signal, the receiver PLL starts locking to the receiver input reference clock. 4.Wait for the rx_freqlocked signal to go high (marker 3). 5.After rx_freqlocked goes high, wait at least 4 Ps and then de-assert the rx_digitalreset signal (marker 4). At this point, the receiver is ready to receive data. Figure4–6.Sample Reset Sequence of Receiver-Only Channel—Receiver CDR in Automatic Lock Mode Reset Signals 2 Output Status Signals 3 4 4 µs busy 1 Two parallel clock cycles rx_analogreset rx_digitalreset rx_freqlocked |
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