Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbo

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Specifications	Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation
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2–56Chapter 2:Transceiver Clocking in ArriaII Devices FPGA Fabric PLL-Transceiver PLL Cascading Arria II Device Handboo

Specifications	Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation
Outline	Arria II Device Handbook Volume 2: Transceivers Contents Chapter Revision Dates Section 1. Transceiver Architecture for Arria II Devices Revision History 1. Transceiver Architecture in Arria II Devices Transceiver Block Overview Clock Multiplier Units (CMU) CMU PLL CMU0 Clock Divider Transceiver Channel Architecture Transmitter Channel Datapath Transmitter PCS TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Receiver PMA Receiver Input Buffer CDR Deserializer Receiver Channel Datapath Calibration Block PCIe Hard IP Block Functional Modes Test Modes Dynamic Reconfiguration Transceiver Port List Document Revision History
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Content	2–56Chapter 2:Transceiver Clocking in ArriaII Devices FPGA Fabric PLL-Transceiver PLL Cascading Arria II Device Handbook Volume 2: TransceiversJune 2011Altera Corporation FPGA Fabric PLL-Transceiver PLL Cascading The CMU PLL synthesizes the input reference clock to generate the high-speed serial clock used in the transmitter PMA. The receiver CDR synthesizes the input reference clock in lock-to-reference mode to generate the high-speed serial clock. This high-speed serial clock output from the CMU PLL and receiver CDR runs at a frequency that is half the configured data rate. The CMU PLLs and receiver CDRs support multiplication factors (M) of 2, 4, 5, 8, 10, 16, 20, and 25. If you use an on-board crystal oscillator to provide the input reference clock through the dedicated REFCLK pins or ITB lines, the allowed crystal frequencies are limited by the CMU PLL and receiver CDR multiplication factors. The input reference clock frequencies are also limited by the allowed phase frequency detector (PFD) frequency range between 50MHz and 325MHz. Example 11: Channel Configuration for 3Gbps Data Rate For a channel configured for 3Gbps data rate, the high-speed serial clock output from the CMU PLL and receiver CDR must run at 1.5Gbps. Table2–16 lists the allowed input reference clock frequencies for Example 11. For a 3Gbps data rate, the QuartusII software allows an input reference clock frequency of 60, 75, 93.75, 150, 187.5, 300, 375, and 750 MHz. To overcome this limitation, Arria II GX and GZ devices allow the synthesized clock output from left corner PLLs in the FPGA fabric to drive the CMU PLL and receiver CDR input reference clock. The additional clock multiplication factors available in the left corner PLLs allow more options for on-board crystal oscillator frequencies. Dedicated Left PLL Cascade Lines Network Arria II GX devices have a dedicated PLL cascade network on the left side of the device that connects to the input reference clock selection circuitry of the CMU PLLs and receiver CDRs. The dedicated PLL cascade network on the left side of the device connects to the input reference clock selection circuitry of the CMU PLLs and receiver CDRs in transceiver blocks located on the left side of the device. Table2–16.Allowed Input Reference Clock Frequencies for Example 11 for Arria II Devices Multiplication Factor (M) On-Board Crystal Reference Clock Frequency (MHz) Allowed with /N = 1With /N = 2 27501500No (1) 4375750No (1) 5300600Yes 8187.5375Yes 10150300Yes 1693.75187.5Yes 2075150Yes 2560120Yes Note to Table2–16: (1)Violates the PFD frequency limit of 325 MHz.
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Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation

Transceivers for the Arria II GX and Arria II GZ Devices Transceivers for the Arria II Device Handbook, Volume 2 Architecture, clocking, CMU, transmitter, receiver, datapath, functional mode, reconfiguration, inte\ rface clocking, PLL Altera Corporation