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| Specifications | Micron technical note discussing point-to-point package aizes and layout basics TN-47-20: Point-to-Point Package Sizes and Layout Basics micron technology; manufacturer; memory; micron; micron technology, inc.; technical note; tech note;\ manufacturer; semiconductors Micron Technology |
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| Specifications | Micron technical note discussing point-to-point package aizes and layout basics TN-47-20: Point-to-Point Package Sizes and Layout Basics micron technology; manufacturer; memory; micron; micron technology, inc.; technical note; tech note;\ manufacturer; semiconductors Micron Technology |
| Outline | Introduction Getting Started-Understand the Packages Special Signals and Designing for Flexibility Design for Debug and/or Test Stub Series Terminated Logic (SSTL_18) General DDR2 Layout Guidelines Match the I/O Drive Keep the traces short Use the Correct Topology Watch Out for Crosstalk Methods of Termination Conclusion Revision History |
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| Content | TN-47-20: Point-to-Point Package Sizes and Layout BasicsIntroduction PDF: 09005aef822d14b5/Source: 09005aef822641f0Micron Technology, Inc., reserves the right to change products or specifications without notice. TN4720.fm-Rev. A 6/07 EN1©2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “as is” basis, without warranties of any kind. Technical Note DDR2 (Point-to-Point) Package Sizes and Layout Basics Introduction Point-to-point designers face many challenges when laying out a new printed circuit board (PCB). The designer may need to arrange groups of devices within a certain area of the PCB, to place components away from critical keep-out zones, include additional solder pads for future component upgrades, or even ensure the design is robust enough to support a potentially faster memory speed. Additional features—like test points, sockets, and alignment holes—may also be needed. Combining these requirements with an already complex PCB floor plan can make a point-to-point layout extremely difficult to complete. DDR2 SDRAM memory can make floor planning easier with the use of JEDEC-standard FBGA packages. The predefined ball out with a simple addressing scheme that supports all densities and configurations helps make it easy to design for future memory upgrades. Another layout advantage of DDR2 memory is support for on-die termination (ODT). ODT improves signal quality while eliminating most of the external parallel termination resistors. By eliminating termination resistors for memory I/O, available board space is increased and the number of through-hole vias is reduced. This document does not go into detail on PCB stack-ups, types of traces (stripline vs. microstrip), or topology characterization for the various nets. This technical note does provide general guidelines for developing the PCB floor plan, points out some of the key features of DDR2 technology, and identifies what to consider when starting a new point- to-point design that uses DDR2 SDRAM devices. A Micron DDR2 design guide containing detailed routing information will soon be available. Getting Started—Understand the Packages One of the first steps to a good design is understanding the package variations that may exist between DDR2 devices. Although all standard packages fall within the JEDEC- defined limits, various package sizes and ball arrays are available. For example, x16 components use either an 84-ball array or a 92-ball array, depending on the overall package size. Likewise, the x4 or x8 configurations use either a 60-ball array or a 68-ball array. Both the 92-ball and 68-ball packages include outrigger balls in each of the four corners. These additional outrigger balls provide mechanical support for the larger package sizes. The center section, or electrical ball array, is identical for the package with outriggers and the package without outriggers. The outrigger balls are true no connects and don’t have any electrical connections to the substrate. |
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| Following Datasheets | 206-208 (4 pages) 206_1 (2 pages) 206282_test_report_rev_1-2-1_1 (62 pages) 206282_test_report_rev_1-2_1 (62 pages) 2064 (14 pages) 206498_LT1475_Do_It_Right_Guide_FRENCH-1 (20 pages) 2064e (11 pages) 2064v (14 pages) 2064ve (17 pages) 2064vl (14 pages) |
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