| Specifications | ispLSI 2064V Data Sheet |
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| Specifications | ispLSI 2064V Data Sheet |
| Business section |
| Specifications | ispLSI 2064V Data Sheet |
| Outline | ispLSI 2064V Data Sheet DC Electrical Characteristics AC Characteristics Pin Configuration: 100 TQFP Pin Configuration: 84 PLCC Pin Configuration: 44 PLCC Pin Configuration: 44 TQFP Ordering Information |
| Suggested Link Details/Purchase | |
| Content | ispLSI ® 2064V 3.3V High Density Programmable Logic 2064v_101 USE ispLSI 2064VE FOR NEW DESIGNS Features •HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic •3.3V LOW VOLTAGE 2064 ARCHITECTURE — Interfaces with Standard 5V TTL Devices — The 64 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2064 •HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 100MHz Maximum Operating Frequency — tpd = 7.5ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power •IN-SYSTEM PROGRAMMABLE —3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic —Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality —Reprogram Soldered Devices for Faster Prototyping •THE EASE OF USE AND FAST SYSTEMSPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity •ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING —Superior Quality of Results —Tightly Integrated with Leading CAE Vendor Tools —Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ —PC and UNIX Platforms Functional Block Diagram Global Routing Pool (GRP)A0 A1 A3 Input Bus Output Routing Pool (ORP) B3 B2 B1 B0 Input Bus Output Routing Pool (ORP) A2GLB Logic Array DQ DQ DQ DQ A4A5A6A7 B7B6B5B4 Input Bus Output Routing Pool (ORP) Input Bus Output Routing Pool (ORP) 0139A/2064V Description The ispLSI 2064V is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064V features in-system programmability through the Boundary Scan Test Ac- cess Port (TAP). The ispLSI 2064V offers non-volatile reprogrammability of the logic, as well as the intercon- nect, to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064V device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064V device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.September 2000 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com |
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| Following Datasheets | 2064ve (17 pages) 2064vl (14 pages) 206644TESTREPORTREV1-1_1 (9 pages) 206ra (2 pages) 207_1 (2 pages) 207134a_rev1-1_test-report (83 pages) 207908CofC_1 (2 pages) 208_1 (4 pages) 208531_SR2010-1 (48 pages) 208774_Code_of_Conduct_and_Annex-1 (58 pages) |
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