Microsoft Word - app-note_PCIE-TH_pci-express-gen3

We use cookies to personalise content and ads, to provide social media features and to analyse traffic. We share info about use of our site with social media, ads and analytics partners. By continuing to browse you are agreeing to use of cookies. See details or close this message.

Page

/21

100%

Specifications	Microsoft Word - app-note_PCIE-TH_pci-express-gen3_final-09-20-2011.doc coreyk
Business section

Application Note Series: PCIE-TH Standard: PCI Express, Generation 3, 8 GT/s Revision Date: 9/20/2011 Copyright 2005 Samtec/T

Specifications	Microsoft Word - app-note_PCIE-TH_pci-express-gen3_final-09-20-2011.doc coreyk
Outline	PCIE-TH Series Final Inch™Designs in PCI Express ApplicationsGeneration 3 - 8.0 GT/s COPYRIGHTS, TRADEMARKS, and PATENTS Terms of Use Disclaimer Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model Figure 1 PCI Express 8 .0 GT/s Test Configuration Abstract Introduction The PCI Express Specification The Simulation Model The Simulation Environment Compliance Eye Mask Compliance Measurements Conclusions
Suggested Link Details/Purchase
Content	Application Note Series: PCIE-TH Standard: PCI Express, Generation 3, 8 GT/s Revision Date: 9/20/2011 Copyright 2005 Samtec/Teraspeed 4 The Simulation Model Figure 1 shows the Samtec PCIE edge-card connector used in a typical multi- segment channel with a source adapter residing on a motherboard and a target adapter residing on an add-in card. The test circuit is modeled as: x Touchstone s-parameter behavioral Tx and Rx package models, as defined by the PCI Express Base Specification, Rev 3.0 for 8.0 GT/s channel compliance testing. x A variable length interconnect trace segment on the source adapter, with and without a 200 nF capacitor x A variable length interconnect trace segment on the target adapter. x A Samtec PCIE edge-card connector touchstone s-parameter. Figure 1 PCI Express 8 .0 GT/s Test Configuration Segment topology of the source and target adapters was swept in multiple ways to determine the limits of compliant channel operation, and whether any sensitivity exists. 1. All combinations of 0.1 to 1 in steps of 0.1 for both the source and target adapter. 2. Source length = target length swept from 1 to 20 to determine the entire reliable operation limit of the channel. 3. Source length swept from 1 to 26 with the target length set at 4 , which is the typical maximum length for PCIE add-in cards.
Navigation	Previous Page / Next Page
Following Datasheets	app-note_PCIEC-1meter_pci-express-gen2_web (17 pages) app-note_PCIE_pci-express-gen2_web (17 pages) app-note_QMS-QFS-16mm_pci-express-gen2_web (16 pages) app-note_QxE-DP-16mm_pci-express-gen2_web (16 pages) app-note_QxH-DP-16mm_pci-express-gen2_web (16 pages) app-note_RU8-30mm_pci-express-gen2_web (16 pages) app-note_xilinx-rocketIO-MGT_with_QxE-FI_EQCDandEQDP_web (10 pages) app_notes_ULN (4 pages) app10_xaui_DPAx (11 pages) Apparent_Impedance_Webinar_062205_rev1 (91 pages)
Check in e-portals	World-H-News Products Extensions Partners Automation Jet Parts
Sitemap Folder	group1 group2 group3 group4 group5 group6 group7 group8 group9 group10 group11 group12 group13 group14 group15 group16 group17 group18 group19 group20 group21 group22 group23 group24 group25 group26 group27 group28 group29 group30 group31 group32 group33 group34 group35 group36 group37 group38 group39 group40 group41 group42 group43 group44 group45 group46 group47 group48 group49 group50 group51 group52 group53 group54 group55 group56 group57 group58 group59 group60 group61 group62 group63 group64 group65 group66 group67 group68 group69 group70 group71 group72 group73 group74 group75 group76 group77 group78 group79 group80 group81 group82 group83 group84 group85 group86 group87 group88 group89 group90 group91 group92 group93 group94 group95 group96 group97 group98 group99 group100 Prewious Folder Next Folder

Microsoft Word - app-note_PCIE-TH_pci-express-gen3_final-09-20-2011.doc coreyk

Microsoft Word - app-note_PCIE-TH_pci-express-gen3_final-09-20-2011.doc coreyk