Thermal Management for Lattice Packaging Thermal Management CSBGA, FCBGA, CABGA, fpSBGA, FTBGA, SBGA

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Specifications	Thermal Management for Lattice Packaging Thermal Management CSBGA, FCBGA, CABGA, fpSBGA, FTBGA, SBGA, TQFP, BGA, PLCC, PQFP, QFN, SSOP, PGA, SOIC, DIP, thermal m\ anagement, junction temperature, case temperature, ambient temperature, Lattice Semiconductor
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www.latticesemi.com1thermal_01.8 Thermal Management February 2012 Introduction Thermal management is recommended as part of a

Specifications	Thermal Management for Lattice Packaging Thermal Management CSBGA, FCBGA, CABGA, fpSBGA, FTBGA, SBGA, TQFP, BGA, PLCC, PQFP, QFN, SSOP, PGA, SOIC, DIP, thermal m\ anagement, junction temperature, case temperature, ambient temperature, Lattice Semiconductor
Outline	Introduction Ways to Reduce Junction Temperature Revision History
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Content	www.latticesemi.com1thermal_01.8 Thermal Management February 2012 Introduction Thermal management is recommended as part of any sound CPLD and FPGA design methodology. To properly assess the thermal characteristics of the system, Lattice Semiconductor specifies a maximum allowable junction temperature in all device data sheets. The system designer should always complete a thermal analysis of their spe- cific design to ensure that the device and package does not exceed the junction temperature requirements. The data shown in this Thermal Management document is relative and actual values depend on a variety of factors such as: die size, paddle size, airflow, power applied, printed circuit board design, proximity of other devices and user applications. Table 1 specifies the generic package thermal resistance for legacy GAL, CPLD, FPGA and XPLD devices. Table 2 specifies the device/package specific thermal resistance for newer FPGA products. These values are based upon JEDEC standards. If specified, the device/package specific thermal value supercedes the generic package thermal data contained in Table 1. In addition to the device and package, the thermal characteristics of a circuit depend on the operating temperature, device power consumption, and the ability of the system to dissipate heat. The maximum junction temperature of a device can be calculated as shown: TJ = TA + PowerTJA or TJ = TA + Power (TJC+RCS+RSA) Where : TJ=Junction Temperature of the Device TA = Ambient Temperature RCS= Thermal resistance of thermal interface material RSA= Thermal resistance of heat sink TJA = Junction-to-Ambient Thermal Resistance (see Tables 1 and 2 at the end of this section) TJC = Junction-to-Case Thermal Resistance (see Tables 1 and 2 at the end of this section) Power = ICC * VCC ICC may be estimated as shown in the “Power Consumption” section of the DC and Switching Characteristics sec- tion of each individual data sheet. The parameters in the ICC equation may be found in the report file from the isp- LEVER® compiler. For predicting power, the best resource is to use ispLEVER design tools. For additional information on power calculations and considerations please refer to the referenced technical note in the For Fur- ther Information section of each individual data sheet. If the calculated TJ max exceeds the specified limits, refer to the following hints to reduce the overall power dissipa- tion and package temperature.
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Thermal Management for Lattice Packaging Thermal Management CSBGA, FCBGA, CABGA, fpSBGA, FTBGA, SBGA, TQFP, BGA, PLCC, PQFP, QFN, SSOP, PGA, SOIC, DIP, thermal m\ anagement, junction temperature, case temperature, ambient temperature, Lattice Semiconductor

Thermal Management for Lattice Packaging Thermal Management CSBGA, FCBGA, CABGA, fpSBGA, FTBGA, SBGA, TQFP, BGA, PLCC, PQFP, QFN, SSOP, PGA, SOIC, DIP, thermal m\ anagement, junction temperature, case temperature, ambient temperature, Lattice Semiconductor

Introduction Ways to Reduce Junction Temperature Revision History