Three-Stating Actel Device I/O Pins for Board Level Testing

We use cookies to personalise content and ads, to provide social media features and to analyse traffic. We share info about use of our site with social media, ads and analytics partners. By continuing to browse you are agreeing to use of cookies. See details or close this message.

Page

100%

Specifications	Three-Stating Actel Device I/O Pins for Board Level Testing
Business section

September 1997 5-141 © 1997 Actel Corporation Three-Stating Actel Device I/O Pins for Board Level Testing Introduction D

Specifications	Three-Stating Actel Device I/O Pins for Board Level Testing
Outline	Three-Stating Actel Device I/O Pins for Board Leve. Introduction ACT 1 Family Three-State Procedure ACT 2, 1200XL, 3200DX, and ACT 3 Families Three-St.
Suggested Link Details/Purchase
Content	September 1997 5-141 © 1997 Actel Corporation Three-Stating Actel Device I/O Pins for Board Level Testing Introduction During board testing and debugging, it is frequently desired or necessary to place all device I/O pins into a three-state, high-impedance condition. This isolates the device from other devices that have common signal paths on a printed circuit board. The three-state condition also allows board testing for trace integrity or insertion damage to pins. It is usually more convenient to simultaneously three-state all I/O pins of a device with a built-in procedure rather than to create test vectors to force this condition by circuit function. All Actel field programmable gate arrays (FPGAs) include a special operating mode to place all I/O pins in a temporary, three-state condition. Thus, each Actel device may be easily isolated from I/O signal paths of other devices on a circuit board, enabling a convenient board testing procedure. This capability, combined with Silicon Explorer diagnostic tools, allows both single device and system board testing with a power and ease previously unavailable in programmable devices. ACT 1 Family Three-State Procedure Three-stating an ACT 1 device is easy using the unique debugging features of the Actel architecture. Three special pins on Actel devices are used for this function: MODE, SDI, and DCLK. To maintain the three-stating feature on ACT 1 devices, no user-defined output or bidirectional pins may be assigned to the SDI and DCLK locations. These pins should remain unassigned or should be defined as input-only locations. All other user-defined pins have no restrictions for their function; they may be assigned as input-only, output-only, or bidirectional pins. These pins can be temporarily three-stated for testing and debugging. Figure 1 shows the sequence for three-stating an ACT 1 device. Seven data bits are clocked into the device using the SDI pin as data input and DCLK as the clock signal. The MODE pin distinguishes “test” mode from “normal” mode. The data sequence is {0001011}. After clocking the seventh bit, all user-defined pins are placed in a three-state condition until MODE is returned to logic low. ACT 2, 1200XL, 3200DX, and ACT 3 Families Three-State Procedure The same special purpose pins are used to three-state ACT 2, 1200XL, 3200DX, and ACT 3 devices: MODE, SDI, and DCLK. In contrast to the ACT 1 family, there are no restrictions on the assignment of user-defined functions to these pins. All user-defined pins have no restrictions for their function; they may be assigned as input-only, output-only, or bidirectional pins. Thirty-two data bits are clocked into the device using the SDI pin as data input and DCLK as the clock signal. The MODE pin distinguishes “test” mode from “normal” mode. The data sequence for ACT 2, 1200XL, 3200DX, and ACT 3 devices is determined by the programmed state of the device. For unprogrammed, blank devices, the data sequence is (LSB) 0000000000 0000000000 0000000111 10 (MSB) For programmed devices, the data sequence is (LSB) 0000000000 0000000000 0000000110 00 (MSB) Load the data beginning with the LSB. After clocking the 32nd bit, all user-defined pins are placed in a three-state condition until MODE is returned to logic low. Use the same relative timing for the MODE, SDI, and DCLK inputs as shown in Figure 1. Application Note AC111
Navigation	Previous Page / Next Page
Suggested Link Details/Purchase

Following Datasheets	threew (1 pages) thrmobnd1500hrdner (4 pages) thrmobnd1500resin (4 pages) thrmobnd1600hrdner (4 pages) thrmobnd1600resin (4 pages) thrmtant (9 pages) Through-Hole-Printing (7 pages) thru-bolt-bracket (1 pages) THW826-4-UltiEVC_Programmer_s_Manual (40 pages) THW829-2-UltiEBB_Programmer_s_Manual (38 pages)
Check in e-portals	World-H-News Products Extensions Partners Automation Jet Parts
Sitemap Folder	group1 group2 group3 group4 group5 group6 group7 group8 group9 group10 group11 group12 group13 group14 group15 group16 group17 group18 group19 group20 group21 group22 group23 group24 group25 group26 group27 group28 group29 group30 group31 group32 group33 group34 group35 group36 group37 group38 group39 group40 group41 group42 group43 group44 group45 group46 group47 group48 group49 group50 group51 group52 group53 group54 group55 group56 group57 group58 group59 group60 group61 group62 group63 group64 group65 group66 group67 group68 group69 group70 group71 group72 group73 group74 group75 group76 group77 group78 group79 group80 group81 group82 group83 group84 group85 group86 group87 group88 group89 group90 group91 group92 group93 group94 group95 group96 group97 group98 group99 group100 Prewious Folder Next Folder

Three-Stating Actel Device I/O Pins for Board Level Testing

Three-Stating Actel Device I/O Pins for Board Level Testing

Three-Stating Actel Device I/O Pins for Board Leve. Introduction ACT 1 Family Three-State Procedure ACT 2, 1200XL, 3200DX, and ACT 3 Families Three-St.