Specifications | The method of wavelet thresholding for removing noise, or denoising, has been researched extensively \ due to its effectiveness and simplicity Amjed Al-Fahoum |
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Specifications | The method of wavelet thresholding for removing noise, or denoising, has been researched extensively \ due to its effectiveness and simplicity Amjed Al-Fahoum |
Business section |
Specifications | The method of wavelet thresholding for removing noise, or denoising, has been researched extensively \ due to its effectiveness and simplicity Amjed Al-Fahoum |
Outline | 1. Introduction 2. 1-D Resampling 3. 2-D Image Resizing 4. 2-D Image Rotation FPGA Implementation Conclusion References |
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Content | BANK 0BANK 1 BANK 4 RAM RAM RAM RAM RAM RAM RAM RAM DLLDLL DLLDLL DLL = DELAY LOCKED LOOP RAM = BLOCK RAM - VARIOUS FORM FACTORS FROM 4096x1 TO 256X16 = 2 SLICE CLB=I/O BANK5 BANK N=MULTI-STANDARD I/O SUPPORT ROUTING Figure 7 Xilinx Virtex FGPA Architecture Alternative algorithms are also available to construct the filtering engine. For example, distributed arithmetic (DA) [9] has been demonstrated to be an extremely useful re- organization of the inner-product equation for FPGA systems. It exploits the look-up table and distributed memory [7] features of the FPGA. Filters and computational units are available from FPGA Vendors (Xilinx CoreGenTM ) as part of the software tool suite for implementation. For the resizing architecture Cores are available for vertical and horizontal functions of Figure 5. This algorithm can be implemented in a single chip device. Depending on the image quality required for the application Xilinx Virtex E part types can range from a XCV300 to XCV1000. Similarly analysis of the rotation architecture of Figure 6 yields Xilinx Virtex E part types ranging from XCV600 to XCV1000. 6. Conclusion In this paper we have discussed the algorithms, architectures, and implementations for image rotation and resizing. Single chip FPGA implementations have been proposed which enable real time processing. Technology advances in the area of embedded memory on FGPAs is particularly attractive to the video and image processing community. Applications in the video communications and medical imaging area can benefit from the real time processing capabilities. Future work in this area will be directed toward image quality issues such as edge preservation and noise characteristics. References [1] Bracewell, R., Two-Dimensional Imaging, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, Inc., 1995. [2] Pratt, W., Digital Image Processing, John Wiley & Sons, Inc., 1991. [3] Gonzalez, R., Wintz, P., Digital Image Processing 2nd Ed., Addison-Wesle, 1987. [4] Gonzalez, R., Woods, R., Digital Image Processing, Addison-Wesley, 1992. [5] Dick, C., harris, f., “FPGA Interpolators Using Polynomial Filters”, The 8th International Conference on Signal Processing Applications and Technology, September 1998. [6] Rasche, V., et al. “Resampling of Data Between Arbitrary Grids Using Convolution Interpolation”, IEEE Transactions on Medical Imaging, Vol. 18, NO. 5, May1999. [7] Xilinx Inc., The Programmable Logic Data Book, 1999. [8] Carey, W., Chuang, D., Hemami, S., “Regular-Preserving Image Interpolation”, IEEE Transactions on Image Processing, Vol. 8, NO. 9, Setpember 1999. [9] S. A. White, “Applications of Distributed Arithmetic to Digital Signal Processing”, IEEE ASSP Magazine, Vol. 6(3), pp. 4-19, July 1989. |
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