| Specifications | SC16C852SV 1.8 V dual UART, 20 Mbit/s \max.\ with 128-byte FIFOs, infrared \IrDA\, and XScale VLI\ O bus interface NXP Semiconductors |
| Business section |
|
|
|
|
|
||||||||||||||||||||||||||||||||||
|
|
|
|
|
||||||||||||||||||||||||||||||||||
| Specifications | SC16C852SV 1.8 V dual UART, 20 Mbit/s \max.\ with 128-byte FIFOs, infrared \IrDA\, and XScale VLI\ O bus interface NXP Semiconductors |
| Business section |
| Specifications | SC16C852SV 1.8 V dual UART, 20 Mbit/s \max.\ with 128-byte FIFOs, infrared \IrDA\, and XScale VLI\ O bus interface NXP Semiconductors |
| Outline | 1. General description 2. Features 3. Ordering information 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 6. Functional description 7. Register descriptions 8. Limiting values 9. Static characteristics 10. Dynamic characteristics 11. Package outline 12. Soldering of SMD packages 13. Abbreviations 14. Revision history 15. Legal information 16. Contact information 17. Contents |
| Suggested Link Details/Purchase | |
| Content | 1.General description The SC16C852SV is a 1.8V, low power dualchannel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 20Mbit/s (4×sampling rate). SC16C852SV can be programmed to operate in extended mode where additional advanced UART features are available (see Section6.2). The SC16C852SV family UART provides enhanced UART functions with 128-byte FIFOs, modem control interface and IrDA encoder/decoder. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specific user requirements. An internal loopback capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C852SV with Intel XScale processor VLIO interface operates at 1.8V and is available in the TFBGA36 package. 2.Features nDual channel high performance UART n1.8V operation nAdvanced package: TFBGA36 nUp to 20Mbit/s data rate (4×sampling) at 1.8V nProgrammable sampling rate: 16×, 8×, 4× n128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU n128-byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU n128 programmable Receive and Transmit FIFO interrupt trigger levels n128 Receive and Transmit FIFO reporting levels (level counters) nAutomatic software (Xon/Xoff) and hardware (RTS/CTS orDTR/DSR) flow control nProgrammable Xon/Xoff characters n128 programmable hardware and software trigger levels nAutomatic 9-bit mode (RS-485) address detection nAutomatic RS-485 driver turn-around with programmable delay nDual channel concurrent write nUART software reset nHigh resolution clock prescaler, from 0 to 15 with granularity of1⁄16 to allow non-standard UART clock to be used SC16C852SV 1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface Rev. 01 — 23 September 2008Product data sheet |
| Navigation | Previous Page / Next Page |
| Following Datasheets | SC16C852V (55 pages) SC16IS740_750_760 (63 pages) SC16IS741 (52 pages) SC16IS752_SC16IS762 (60 pages) SC16IS850L (60 pages) SC18IM700 (22 pages) SC18IS600_601 (30 pages) SC18IS602B (25 pages) SC18_1999_CHAPTER_5_2 (24 pages) SC26C92 (31 pages) |
Check in e-portals |
World-H-News Products Extensions Partners Automation Jet Parts |
| Sitemap Folder | group1 group2 group3 group4 group5 group6 group7 group8 group9 group10 group11 group12 group13 group14 group15 group16 group17 group18 group19 group20 group21 group22 group23 group24 group25 group26 group27 group28 group29 group30 group31 group32 group33 group34 group35 group36 group37 group38 group39 group40 group41 group42 group43 group44 group45 group46 group47 group48 group49 group50 group51 group52 group53 group54 group55 group56 group57 group58 group59 group60 group61 group62 group63 group64 group65 group66 group67 group68 group69 group70 group71 group72 group73 group74 group75 group76 group77 group78 group79 group80 group81 group82 group83 group84 group85 group86 group87 group88 group89 group90 group91 group92 group93 group94 group95 group96 group97 group98 group99 group100 Prewious Folder Next Folder |
