SC16C754B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s \max.\ with 64-byte FIFOs NXP Semiconductors

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Specifications	SC16C754B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s \max.\ with 64-byte FIFOs NXP Semiconductors
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1.General description TheSC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic

Specifications	SC16C754B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s \max.\ with 64-byte FIFOs NXP Semiconductors
Outline	1. General description 2. Features 3. Ordering information 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 4. Block diagram 5. Pinning information 6. Functional description 7. Register descriptions 8. Programmer’s guide 9. Limiting values 10. Static characteristics 11. Dynamic characteristics 12. Package outline 13. Soldering of SMD packages 14. Abbreviations 15. Revision history 16. Legal information 17. Contact information 18. Contents
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Content	1.General description TheSC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software ﬂow control, and data rates up to 5Mbit/s (3.3Vand5V).TheSC16C754Boffersenhancedfeatures.IthasaTransmissionControl Register(TCR)thatstoresreceiverFIFOthresholdlevelstostart/stoptransmissionduring hardware and software ﬂow control. With the FIFO Ready (FIFORdy) register, the softwaregetsthestatusofTXRDY/RXRDYforallfourportsinoneaccess.On-chipstatus registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics. The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8bits.TheUARThasa64-bytereceiveFIFOandtransmitFIFOandcanbeprogrammed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overﬂow, and parity errors. The transmitter can detect FIFO underﬂow. The UART also contains a software interface for modem control operations, and has software ﬂow control and hardware ﬂow control capabilities. TheSC16C754B is available in plastic LQFP64, LQFP80 and PLCC68 packages. 2.Features n4 channel UART n5V, 3.3V and 2.5V operation nPin compatible with SC16C654IA68, TL16C754, and SC16C554IA68 with additional enhancements, and software compatible with TL16C754 nUp to 5Mbit/s data rate (at 3.3V and 5V; at 2.5V maximum data rate is 3Mbit/s) n5V tolerant on input only pins1 n64-byte transmit FIFO n64-byte receive FIFO with error ﬂags nIndustrial temperature range (−40°C to +85°C) nProgrammable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation SC16C754B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 04 — 6 October 2008Product data sheet 1.For data bus pins D7 to D0, seeTable 24 “Limiting values”.
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