DS430 OPB 16550 UART DS430 OPB 16550 UART DS430 OPB 16550 UART Xilinx, Inc.

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Specifications	DS430 OPB 16550 UART DS430 OPB 16550 UART DS430 OPB 16550 UART Xilinx, Inc.
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0 OPB 16550 UART (v1.00d) DS430 December 2, 200500Product Specification DS430 December 2, 2005www.xilinx.com1 Product Specifi

Specifications	DS430 OPB 16550 UART DS430 OPB 16550 UART DS430 OPB 16550 UART Xilinx, Inc.
Outline	OPB 16550 UART (v1.00d) Introduction Features Functional Description OPB 16550 UART Design Parameters Allowable Parameter Combinations OPB 16550 UART I/O Signals Parameter - Port Dependencies OPB 16550 UART Register Definition OPB 16550 UART Interface OPB 16550 UART Register Logic OPB_IPIF IPIC_IF UART16550 User Application Hints Design Implementation Target Technology Device Utilization and Timing Performance Benchmarks Specification Exceptions FIFO Control Register System Clock Register Addresses Reference Documents Revision History
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Content	0 OPB 16550 UART (v1.00d) DS430 December 2, 200500Product Specification DS430 December 2, 2005www.xilinx.com1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction This document provides the specification for the OPB 16550 UART (Universal Asynchronous Receiver/Transmitter) Intellectual Property (IP). The OPB 16550 UART described in this document has been designed incorporating features described in National Semiconductor PC16550D UART with FIFOs data sheet (June,1995), (http://www.national.com/pf/PC/PC16550D.html). The National Semiconductor PC16550D data sheet is referenced throughout this document and should be used as the authoritative specification. Differences between the National Semiconductor implementation and the OPB 16550 UART Point Design implementation are highlighted and explained in Specification Exceptions. Features •Hardware and software register compatible with all standard 16450 and 16550 UARTs •Implements all standard serial interface protocols -5, 6, 7, or 8 bits per character -Odd, Even, or no parity detection and generation -1, 1.5, or 2 stop bit detection and generation -Internal baud rate generator and separate receiver clock input -Modem control functions -False start bit detection and recovery -Prioritized transmit, receive, line status, and modem control interrupts -Line break detection and generation -Internal loop back diagnostic functionality -Independent 16 word transmit and receive FIFOs LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-E Version of Coreopb_uart16550v1.00d Resources Used MinMax Slices283417 LUTs328545 FFs275338 Block RAMs Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsNone Design Tool Requirements Xilinx Implementation ToolsISE 6.1i or later VerificationModelSim SE/EE 5.8e or later SimulationModelSim SE/EE 5.8e or later SynthesisXST Support Support provided by Xilinx, Inc. Discontinued IP
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