DS433 OPB 16450 UART DS433 OPB 16450 UART DS433 OPB 16450 UART Xilinx, Inc.

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Specifications	DS433 OPB 16450 UART DS433 OPB 16450 UART DS433 OPB 16450 UART Xilinx, Inc.
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0 OPB 16450 UART DS433 August 18, 200400Product Specification DS433 August 18, 2004www.xilinx.com1 Product Specification1-800

Specifications	DS433 OPB 16450 UART DS433 OPB 16450 UART DS433 OPB 16450 UART Xilinx, Inc.
Outline	OPB 16450 UART Introduction Features UART Background Parameter - Port Dependencies UART Register Definition UART Interface (IPIF) UART Register Logic Receiver Buffer Register Transmitter Buffer Register Interrupt Enable Register Interrupt Identification Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor (Least Significant Byte) Register Divisor (Most Significant Byte) Register
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Content	0 OPB 16450 UART DS433 August 18, 200400Product Specification DS433 August 18, 2004www.xilinx.com1 Product Specification1-800-255-7778 © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction This document provides the specification for the OPB Uni- versal Asynchronous Receiver/Transmitter (UART) Intellec- tual Property (IP). The UART described in this document has been designed incorporating the features described in National Semicon- ductor PC16550D UART with FIFOs data sheet (June, 1995), (http://www.national.com/pf/PC/PC16550D.html). The National Semiconductor PC16550D data sheet is refer- enced throughout this document and should be used as the authoritative specification. Differences between the National Semiconductor implementation and the OPB UART Point Design implementation are highlighted and explained in Specification Exceptions Features •Hardware and software register compatible with all standard 16450 UARTs •Implements all standard serial interface protocols -5, 6, 7, or 8 bits per character -Odd, Even, or no parity detection and generation -1, 1.5, or 2 stop bit detection and generation -Internal baud rate generator and separate receiver clock input -Modem control functions -False start bit detection and recovery -Prioritized transmit, receive, line status, and modem control interrupts -Line break detection and generation -Internal loop back diagnostic functionality •Registers -Receiver Buffer Register (Read Only) -Transmitter Holding Register (Write Only) -Interrupt Enable Register -Interrupt Identification Register (Read Only) -Line Control and Line Status Registers -Modem Control and Modem Status Registers •Scratch Register LogiCORE™ Facts Core Specifics Supported Device Family Virtex-II Pro™, Virtex™, Virtex-II™, Virtex-4™, QPro™-R Virtex-II, QPro Virtex-II, Virtex-E, Spartan-II™, Spartan-IIE™, Spartan-3™ Version of Coreopb_uart16450v1.00c Resources Used MinMax Slices341341 LUTs357357 FFs347347 Block RAMs00 Provided with Core DocumentationProduct Specification. Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation Template N/A Reference DesignsNone Design Tool Requirements Xilinx Implementation Tools 5.1i or later VerificationN/A SimulationModelSim SE/EE 5.6e or later SynthesisXST Support Support provided by Xilinx, Inc. -Divisor Latch (least and more significant byte) Discontinued IP
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