DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Se

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Specifications	DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ Xilinx, Inc
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0 OPB Serial Peripheral Interface (SPI) (v1.00e) DS464 July 21, 200600Product Specification DS464 July 21, 2006www.xilinx.com

Specifications	DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ Xilinx, Inc
Outline	OPB Serial Peripheral Interface (SPI) (v1.00e) Introduction Features Functional Description OPB SPI I/O Signals OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Target Technology EEPROM Test Matrix for Virtex-II Pro (XC2VP7-5-FF672) Device Utilization and Performance Benchmarks OPB SPI Design Parameters Parameter-Port Dependencies OPB SPI Register Descriptions IPIF Software Reset Register SPI Control Register (SPICR) SPI Status Register (SPISR) SPI Data Transmit Register (SPIDTR) SPI Data Receive Register (SPIDRR) SPI Slave Select Register (SPISSR) SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY) SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY) OPB SPI Interrupt Descriptions Design Implementation Specification Exceptions Reference Documents Revision History
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Content	0 OPB Serial Peripheral Interface (SPI) (v1.00e) DS464 July 21, 200600Product Specification DS464 July 21, 2006www.xilinx.com1 Product Specification © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The Xilinx OPB Serial Peripheral Interface (SPI) connects to the OPB and provides the controller interface to any SPI device such as SPI EEPROMs. It is assumed that the reader is familiar with the SPI EEPROMs and its operation. The OPB SPI is based on the Motorola M68HC11 device. However, there are differences in Xilinx OPB SPI implementation and the M68HC11 specification that should be reviewed, see the Specification Exceptions section. Features The Xilinx OPB SPI is a soft IP core designed for the Xilinx FPGAs and contains following features: •Supports four signal interface (MOSI, MISO, SCK and SS) •Supports slave select (SS) bit for each slave on the SPI bus •Supports full-duplex operation •Supports master and slave SPI modes •Supports programable clock phase and polarity •Optional transmit and receive FIFOs •Supports continuous transfer mode for automatic scanning of a peripheral •Supports back-to-back transactions •Supports automatic or manual slave select modes •Supports local loopback capability for testing LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex-II™, QPro Virtex-II, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-3 and Virtex-5 Version of Coreopb_spiv1.00e Resources Used. MinMin Slices See Table 16 and Table 17LUTs FFs Block RAMs Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsNone Design Tool Requirements Xilinx Implementation Tools8.2i or later VerificationModelSim SE 6.0 or later SimulationModelSim SE 6.0 or later SynthesisXST 8.2i or later Support Support provided by Xilinx, Inc. Discontinued IP
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DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ Xilinx, Inc

DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ DS464 OPB Serial Peripheral Interface \SPI\ Xilinx, Inc