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| Outline | OPB Monitor BFM Introduction Features More Information Implementation MPD Parameters Revision History |
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| Content | DS130 (v2.0) April 30, 2004www.xilinx.com1 Product Overview1-800-255-7778 ©2004Xilinx,Inc.Allrightsreserved.AllXilinxtrademarks,registeredtrademarks,patents,andfurtherdisclaimersareaslistedathttp://www.xilinx.com/legal.htm.Allother trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICEOFDISCLAIMER:Xilinxisprovidingthisdesign,code,orinformation asis. Byprovidingthedesign,code,orinformationasonepossibleimplementationofthisfeature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may requireforyourimplementation.Xilinxexpresslydisclaimsanywarrantywhatsoeverwithrespecttotheadequacyoftheimplementation,includingbutnotlimitedtoanywarranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction TheCoreConnectToolkitOPBMonitorBusFunctional Modelisasimulationhardwarecomponentthatconnectsto the OPB and continuously samples the bus signals. Themonitorchecksforbuscomplianceorviolationsofthe OPBarchitecturalspecificationsandreportswarningsand errors. Features •Xilinx OPB bus interface •Checks for bus compliance or violations •Reports warnings and errors •BehaviorconfiguredinaBusFunctionalLanguage (BFL) file More Information FordetailedinformationontheIBMOPBBusFunctional ModelToolkit,youmayregisterfortheCoreConnectLounge ontheXilinxwebsitetogetaccesstotheIBMCoreConnect documentation. 0 OPB Monitor BFM DS130 (v2.0) April 30, 200400Product Overview Core Facts Core Specifics Supported Device FamilyAll Version of Coreopb_monitor _bfm v1.00.a Resources Used MinMax I/ON/AN/A LUTsN/AN/A FFsN/AN/A Block RAMsN/AN/A Provided with Core DocumentationThis document Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation Template N/A Reference DesignsNone Design Tool Requirements XilinxImplementation Tools EDK 6.2 or later ISE 6.2 or later VerificationN/A SimulationModelSim SE/EE 5.6e or later SynthesisN/A Support Support provided by Xilinx, Inc. Discontinued IP |
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| Following Datasheets | opb_opb_lite (6 pages) opb_pci (70 pages) opb_pci_arbiter (9 pages) opb_plbv46_bridge (12 pages) opb_sdram (32 pages) opb_spi (31 pages) opb_sysace (11 pages) opb_timebase_wdt (9 pages) opb_timer (13 pages) opb_uart16450 (15 pages) |
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