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| Specifications | Untitled Document |
| Business section |
| Specifications | Untitled Document |
| Outline | Microprocessor Debug Module (MDM) Introduction Features MDM Design Parameters Number of MicroBlaze ports UART Interface UART data width Revision History |
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| Content | DS450 (v1.1) March 26, 2003www.xilinx.com1 Product Overview1-800-255-7778 © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction This document provides the design specification for the Microblaze Debug Module (MDM). The MDM core enables JTAG-based debugging of one or more MicroBlaze proces- sors. Features •Support for JTAG-based software debug tools •Support for debugging a configurable number of MicroBlaze processors •Support for synchronized control of multiple MicroBlaze processors - stop and single step •Support for a JTAG-based UART with an OPB interface •Based on BSCAN logic in Xilinx FPGAs •Supports connection to Chipscope ICON core through unused BSCAN signals 0 Microprocessor Debug Module (MDM) DS450 (v1.1) March 26, 200300Product Overview LogiCORE™ Facts Core Specifics Supported Device FamilyTBD Version of Coreopb_mdmv1.00.c Resources Used MinMax SlicesTBDTBD LUTsTBDTBD FFsTBDTBD Block RAMsTBDTBD Provided with Core DocumentationProduct Specification Design File FormatsTBD Constraints FileTBD VerificationTBD Instantiation Template TBD Reference DesignsTBD Design Tool Requirements Xilinx Implementation Tools TBD VerificationTBD SimulationModelSim SE/EE 5.6e or later SynthesisXST Support Support provided by Xilinx, Inc. |
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| Following Datasheets | opb_monitor_bfm (2 pages) opb_opb_lite (6 pages) opb_pci (70 pages) opb_pci_arbiter (9 pages) opb_plbv46_bridge (12 pages) opb_sdram (32 pages) opb_spi (31 pages) opb_sysace (11 pages) opb_timebase_wdt (9 pages) opb_timer (13 pages) |
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