ds404 OPB IPIF ds404 OPB IPIF ds404 OPB IPIF Xilinx, Inc.

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Specifications	ds404 OPB IPIF ds404 OPB IPIF ds404 OPB IPIF Xilinx, Inc.
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0 OPB IPIF (v3.01c) DS414 December 2, 200500Product Specification DS414 December 2, 2005www.xilinx.com1 Product Specification

Specifications	ds404 OPB IPIF ds404 OPB IPIF ds404 OPB IPIF Xilinx, Inc.
Outline	OPB IPIF (v3.01c) Introduction Features OPB IPIF Overview OPB IPIF Parameters OPB IPIF Parameter Detailed Descriptions Address Range Definition Arrays C_ARD_ID_ARRAY C_ARD_ADDR_RANGE_ARRAY C_ARD_DWIDTH_ARRAY C_ARD_NUM_CE_ARRAY C_ARD_DEPENDENT_PROPS_ARRAY C_DEV_BLK_ID C_DEV_MIR_ENABLE C_DEV_BURST_ENABLE C_PIPELINE_MODEL C_INCLUDE_ADDR_CNTR C_INCLUDE_WR_BUF C_IP_INTR_MODE_ARRAY C_OPB_AWIDTH C_OPB_DWIDTH C_FAMILY
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Content	0 OPB IPIF (v3.01c) DS414 December 2, 200500Product Specification DS414 December 2, 2005www.xilinx.com1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The OPB IPIF is a continuation of the Xilinx family of IBM CoreConnect™ compatible LogiCORE™ products. It pro- vides a bidirectional interface between a user IP core and the OPB 32-bit bus standard. The Xilinx OPB IPIF is avail- able for use with various FPGA device families that support embedded hard or soft processors. Features •Compatible with IBM CoreConnect 32-bit OPB. •Supports user IP data widths from 8 bits to 32 bits with automatic byte steering. •Extensive user customizing support via HDL parameterization. user optioned services include: -Local IP Interrupt collection with user S/W programmable enables/disables. -user S/W triggered reset generator for localized reset of user’s core. -Sequential-Address transfer support. -user configured WrFIFO with optional IP packet support. -user configured RdFIFO with optional IP packet support. LogiCORE Facts Core Specifics Supported Device Family Spartan-II™, Spartan-IIE, Spartan-3, Spartan-3E, Virtex™, Virtex-II, Virtex-II Pro, Virtex-E Version of Coreopb_ipifv3.01c Resources Used MinMax Slices27544 LUTs9845 FFs36441 Block RAMs04 Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileNone VerificationEDK Simulation Support Instantiation Template Wizard Support Reference DesignsN/A Design Tool Requirements Xilinx Implementation Tools Xilinx EDK 6.2.2 VerificationModelSim SE 5.7b or later SimulationModelSim SE 5.7b or later Discontinued IP
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Following Datasheets	opb_mdm (3 pages) opb_monitor_bfm (2 pages) opb_opb_lite (6 pages) opb_pci (70 pages) opb_pci_arbiter (9 pages) opb_plbv46_bridge (12 pages) opb_sdram (32 pages) opb_spi (31 pages) opb_sysace (11 pages) opb_timebase_wdt (9 pages)
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