OPB IIC Bus interface, Product Specification OPB IIC Bus interface OPB IIC Bus interface,Xilinx,IP,L

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Specifications	OPB IIC Bus interface, Product Specification OPB IIC Bus interface OPB IIC Bus interface,Xilinx,IP,LogiCORE,Spartan,Virtex,cores,DS434,434 Xilinx, Inc.
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DS434 May 23, 2006www.xilinx.com1 Product Specification © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks,

Specifications	OPB IIC Bus interface, Product Specification OPB IIC Bus interface OPB IIC Bus interface,Xilinx,IP,LogiCORE,Spartan,Virtex,cores,DS434,434 Xilinx, Inc.
Outline	OPB IIC Bus Interface (v1.01d) Introduction Features Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description IIC Protocol Functional Description OPB IIC Design Parameters OPB IIC I/O Signals OPB IIC Port Dependencies OPB IIC Register Descriptions OPB IIC Interrupt Descriptions Flow Description Throttle Description Design Implementation Specification Exceptions Reference Documents Revision History
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Content	DS434 May 23, 2006www.xilinx.com1 Product Specification © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction This product specification defines the architecture and interface requirements for OPB IIC module. This includes registers that must be initialized for proper operation. OPB IIC module supports all features, except high speed mode, of the Philips IIC bus, v2.1, release January 2000. See the Specification Exceptions section for more details. The Xilinx OPB IIC soft IP core design allows the customer to tailor the OPB IIC to suit their application by setting certain parameters to enable/disable features. The parameterizable features of the design are discussed in the OPB IIC Design Parameters section. Features •Master or Slave operation •Multi-master operation •Software selectable acknowledge bit •Arbitration lost interrupt with automatic mode switching from Master to Slave •Calling address identification interrupt with automatic mode switching from Master to Slave •START and STOP signal generation/detection •Repeated START signal generation •Acknowledge bit generation/detection •Bus busy detection •Fast Mode 400 KHz operation or Standard Mode 100 KHz •7 Bit or 10 Bit addressing •General Call Enable or Disable •Transmit and Receive FIFOs - 16 bytes deep •Throttling •General Purpose Output, zero to 8 bits wide 0 OPB IIC Bus Interface(v1.01d) DS434 May 23, 200600Product Specification LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-E Version of CoreOPB_IICv1.01d Resources Used MinMax I/O22 LUTs353374 FFs203210 BRAMs00 Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsN/A Design Tool Requirements Xilinx Implementation Tools ISE 6.1 or later with latest EDK VerificationModelSim SE/EE 5.8 or later SimulationModelSim SE/EE 5.8 or later SynthesisXST 6.1 or later Support Support provided by Xilinx, Inc. Discontinued IP
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Following Datasheets	opb_intc (21 pages) opb_ipif (61 pages) opb_mdm (3 pages) opb_monitor_bfm (2 pages) opb_opb_lite (6 pages) opb_pci (70 pages) opb_pci_arbiter (9 pages) opb_plbv46_bridge (12 pages) opb_sdram (32 pages) opb_spi (31 pages)
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OPB IIC Bus interface, Product Specification OPB IIC Bus interface OPB IIC Bus interface,Xilinx,IP,LogiCORE,Spartan,Virtex,cores,DS434,434 Xilinx, Inc.

OPB IIC Bus interface, Product Specification OPB IIC Bus interface OPB IIC Bus interface,Xilinx,IP,LogiCORE,Spartan,Virtex,cores,DS434,434 Xilinx, Inc.