| Specifications | ds441 OPB Ethernet Lite Media Access Controller ds441 OPB Ethernet Lite Media Access Controller ds441 OPB Ethernet Lite Media Access Controller Xilinx, Inc. |
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| Specifications | ds441 OPB Ethernet Lite Media Access Controller ds441 OPB Ethernet Lite Media Access Controller ds441 OPB Ethernet Lite Media Access Controller Xilinx, Inc. |
| Business section |
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| Specifications | ds441 OPB Ethernet Lite Media Access Controller ds441 OPB Ethernet Lite Media Access Controller ds441 OPB Ethernet Lite Media Access Controller Xilinx, Inc. |
| Outline | OPB Ethernet Lite Media Access Controller (v1.01b) Introduction Features Functional Description Ethernet Protocol Processor Interface OPB Ethernet Lite MAC Design Parameters Allowable Parameter Combinations OPB Ethernet Lite MAC I/O Signals OPB Ethernet Lite MAC Port Dependencies Clocks Transmit Clock Receive Clock Processor Bus Clock PHY Interface Signals PHY_RST_N TX_EN TXD(3:0) RX_DV RXD(3:0) RX_ER CRS COL Receive Address Validation Design Constraints Design Implementation Design Tools Target Technology Device Utilization and Performance Benchmarks Specification Exceptions No Exceptions Reference Documents Revision History |
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| Content | 0 OPB Ethernet Lite Media Access Controller (v1.01b) DS441 March 3, 200600Product Specification DS441 March 3, 2006www.xilinx.com1 Product Specification © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. Differences between the IEEE Std. 802.3 MII interface specification and the Xilinx Ethernet Lite MAC implementation are highlighted and explained in the Specification Exceptions section. The Ethernet Lite MAC Interface design is a soft intellectual property (IP) core designed for implementation in selected Xilinx Virtex and Spartan family FPGAs. The Ethernet Lite MAC supports the IEEE Std. 802.3 Media Independent Interface (MII) to industry standard Physical Layer (PHY) devices and communicates to a processor via an IBM On-Chip Peripheral Bus (OPB) interface. The design provides a 10 Megabits per second (Mbps) and 100 Mbps (also known as Fast Ethernet) Interface. The goal is to provide the minimal functions necessary to provide an Ethernet interface with the least resources used. Features •32-bit OPB slave interface •Memory mapped direct I/O interface to the transmit and receive data dual port memory •Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers •Independent internal 2K byte Tx and Rx dual port memory for holding data for one packet each CSMA/CD com •Optional dual buffer memories, 4K byte ping-pong, for Tx and Rx LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-E Version of Coreopb_ethernetlitev1.01b Resources Used MinMax I/O99100 LUTs549721 FFs313376 Block RAMs24 Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsN/A Design Tool Requirements Xilinx Implementation Tools6.2i or later VerificationModelSim SE/EE 5.8b or later SimulationModelSim SE/EE 5.8b or later SynthesisXST Support Provided by Xilinx, Inc. •Receive and Transmit Interrupts -Individual interrupt enable for Receive and Transmit -Global device interrupt enable Discontinued IP |
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| Following Datasheets | opb_hwicap (7 pages) opb_iic (20 pages) opb_intc (21 pages) opb_ipif (61 pages) opb_mdm (3 pages) opb_monitor_bfm (2 pages) opb_opb_lite (6 pages) opb_pci (70 pages) opb_pci_arbiter (9 pages) opb_plbv46_bridge (12 pages) |
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