Design Document OPB External Peripheral Controller \EPC\ \v1.00a\ DS325,OPB External Peripheral Cont

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Specifications	Design Document OPB External Peripheral Controller \EPC\ \v1.00a\ DS325,OPB External Peripheral Controller \EPC\ \v1.00a\,FPGA,Xilinx,Virtex,Spartan,SMSC LAN91C111\ ,IP Xilinx, Inc.
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0 OPB External Peripheral Controller (EPC) v1.00a DS325 August 10, 200700Product Specification DS325 August 10, 2007www.xilin

Specifications	Design Document OPB External Peripheral Controller \EPC\ \v1.00a\ DS325,OPB External Peripheral Controller \EPC\ \v1.00a\,FPGA,Xilinx,Virtex,Spartan,SMSC LAN91C111\ ,IP Xilinx, Inc.
Outline	OPB External Peripheral Controller (EPC) v1.00a Introduction Features Functional Description OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB_IPIF EPC_CORE OPB EPC Design Description OPB EPC I/O Signals OPB EPC Design Parameters OPB EPC External Peripheral Connections Design Constraints Design Implementation Reference Documents Revision History
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Content	0 OPB External Peripheral Controller (EPC) v1.00a DS325 August 10, 200700Product Specification DS325 August 10, 2007www.xilinx.com1 Product Specification © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC). The controller supports data transfers between the On-Chip Peripheral Bus (OPB) and the external synchronous and/or asynchronous peripheral devices. Examples of peripheral devices supported by the EPC include the 10/100 non-PCI Ethernet single chip (SMSC LAN91C111) from SMSC and CY7C67300 USB Controller from Cypress Semiconductor devices. Features •OPB v2.0 bus interface with byte-enable support •Parameterized support of up to four external peripheral devices with each device configured with separate base address and high address range •Supports both synchronous and asynchronous access modes of peripheral devices with the support for a separate clock domain for synchronous peripheral devices •Supports both multiplexed and non-multiplexed address and data buses •The data width of peripheral devices is independently configured to 8-bit, 16-bit or 32-bit with the provision to enable data width matching when the OPB data width is greater than that of peripheral device •Configurable timing parameters for peripheral bus interface •Tested with the SMSC LAN91C111 and the Cypress CY7C67300 USB Controller device •OPB slave only device LogiCORE™ Facts Core Specifics Supported Device Family Virtex™-II, Virtex-II Pro, Virtex-4, Spartan™-3 and Virtex-5 Version of Coreopb_epcv1.00a Resources Used MinMax Slices Refer Table 6 & Table 7LUTs FFs Block RAMsNANA Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsNone Design Tool Requirements Xilinx Implementation ToolsISE 8.2i or later VerificationModelSim SE/EE 6.0c or later SimulationModelSim SE/EE 6.0c or later SynthesisXST 8.2i or later Support Support provided by Xilinx, Inc. Discontinued IP
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Following Datasheets	opb_ethernet (54 pages) opb_ethernetlite (23 pages) opb_hwicap (7 pages) opb_iic (20 pages) opb_intc (21 pages) opb_ipif (61 pages) opb_mdm (3 pages) opb_monitor_bfm (2 pages) opb_opb_lite (6 pages) opb_pci (70 pages)
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Design Document OPB External Peripheral Controller \EPC\ \v1.00a\ DS325,OPB External Peripheral Controller \EPC\ \v1.00a\,FPGA,Xilinx,Virtex,Spartan,SMSC LAN91C111\ ,IP Xilinx, Inc.

Design Document OPB External Peripheral Controller \EPC\ \v1.00a\ DS325,OPB External Peripheral Controller \EPC\ \v1.00a\,FPGA,Xilinx,Virtex,Spartan,SMSC LAN91C111\ ,IP Xilinx, Inc.