| Specifications | OPB Delta-Sigma DAC OPB Delta-Sigma DAC OPB Delta-Sigma DAC Xilinx, Inc. |
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| Specifications | OPB Delta-Sigma DAC OPB Delta-Sigma DAC OPB Delta-Sigma DAC Xilinx, Inc. |
| Business section |
| Specifications | OPB Delta-Sigma DAC OPB Delta-Sigma DAC OPB Delta-Sigma DAC Xilinx, Inc. |
| Outline | OPB Delta-Sigma DAC (v1.01a) Introduction Features Functional Description Delta-Sigma Architecture OPB Delta-Sigma DAC I/O Signals Delta-Sigma DAC Design Parameters Allowable Parameter Combinations OPB Delta-Sigma DAC Port Dependencies OPB Delta-Sigma DAC Register Descriptions Control Register (cr_i) Data FIFO Data FIFO Occupancy Register (OCCY) Data FIFO Programmable Depth Interrupt Register (PIRQ) OPB Delta-Sigma DAC Interrupt Descriptions Interrupts Flow Description Design Implementation Design Tools Target Technology Device Utilization and Performance Benchmarks Reference Documents Revision History |
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| Content | 0 OPB Delta-Sigma DAC (v1.01a) DS487 December 1, 200500Product Specification DS487 December 1, 2005www.xilinx.com1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction Digital to analog converters (DACs) convert a binary number into a voltage directly proportional to the value of the binary number. A variety of applications use DACs including waveform generators and programmable voltage sources. The only external circuitry required is a low pass filter comprised of just one resistor and one capacitor. Features •Selectable DAC width •Selectable full scale output •Programmable interrupt generation •16 entry deep data FIFO •32 bit OPB slave interface LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-E Version of Coreopb_deltasigma _dacv1.01a Resources Used MinMax I/Os8092 LUTs114156 FFs81148 Block RAMsN/AN/A Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsN/A Design Tool Requirements Xilinx Implementation Tools ISE 6.2i or later with latest EDK VerificationModelSim SE 5.8b or later SimulationModelSim SE 5.8b or later SynthesisXST - ISE 6.2i Support Support provided by Xilinx, Inc. Discontinued IP |
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| Following Datasheets | opb_device_bfm (2 pages) opb_emc (34 pages) opb_epc (45 pages) opb_ethernet (54 pages) opb_ethernetlite (23 pages) opb_hwicap (7 pages) opb_iic (20 pages) opb_intc (21 pages) opb_ipif (61 pages) opb_mdm (3 pages) |
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