| Specifications | Virtex Analog to Digital Converter Virtex Analog to Digital Converter Virtex Analog to Digital Converter Xilinx, Inc |
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| Specifications | Virtex Analog to Digital Converter Virtex Analog to Digital Converter Virtex Analog to Digital Converter Xilinx, Inc |
| Business section |
| Specifications | Virtex Analog to Digital Converter Virtex Analog to Digital Converter Virtex Analog to Digital Converter Xilinx, Inc |
| Outline | OPB Delta-Sigma Analog to Digital Converter (ADC) (v1.01a) Introduction Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters Allowable Parameter Combinations Features OPB ADC Design Parameters OPB ADC I/O Signals OPB ADC Parameter - Port Dependencies OPB ADC Register Descriptions OPB ADC Block Diagram Timing Diagram of OPB ADC Design Implementation Reference Documents Revision History |
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| Content | 0 OPB Delta-Sigma Analog to Digital Converter (ADC) (v1.01a) DS488 December 1, 200500Product Specification DS488 December 1, 2005www.xilinx.com1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS Introduction When digital systems are used in real-world applications, it is often necessary to convert an analog voltage level to a binary number. The value of this number is directly or inversely proportional to the voltage. The analog to digital conversion is realized in the OPB Delta-Sigma ADC (OPB ADC) using Delta-Sigma conversion techniques. This soft IP core is designed to interface with the OPB (On-chip Peripheral Bus). Features •32 bit OPB slave interface •Supports single beat transactions •OPB Latency <= 3 Clock cycles •able to operate at OPB Clock frequency >= 100MHz •16 entry deep data FIFO •Selectable ADC resolution Figure 1 shows how a typical implementation of analog to digital conversion is performed using the OPB ADC. A Delta-Sigma DAC, which is a primary block of the OPB ADC core, is used to generate a reference voltage ADCref for the negative input to the external comparator. The analog signal, AnalogIn, feeds the positive input of the comparator. The voltage range of the Delta-Sigma DAC out- put is 0V to VCCO, where Vcco is the supply voltage applied to the FPGA I/O bank. This is also the range of analog volt- age that can be converted. If the analog input voltage is outside the range 0V to VCCO, either the Delta-Sigma DAC output or the analog signal itself may be biased, attenuated, or amplified with external components to achieve the desired voltage range compati- bility. The analog voltage level is determined by performing a serial binary voltage search, starting at the middle of the voltage range. LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-E Version of Coreopb_deltasigma _adcv1.01a Resources Used MinMax SLICES191209 LUTs199229 FFs239253 Block RAMsN/AN/A Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation Template N/A Reference Designs Design Tool Requirements Xilinx Implementation Tools ISE 6.1i SP1 or later VerificationModelSim SE/EE 5.8e or later SimulationModelSim SE/EE 5.8e or later SynthesisXST Support Support provided by Xilinx, Inc. Discontinued IP |
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| Following Datasheets | opb_deltasigma_dac (19 pages) opb_device_bfm (2 pages) opb_emc (34 pages) opb_epc (45 pages) opb_ethernet (54 pages) opb_ethernetlite (23 pages) opb_hwicap (7 pages) opb_iic (20 pages) opb_intc (21 pages) opb_ipif (61 pages) |
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