DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller DS425 PLB Double Data Rate \DDR

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Specifications	DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller PLB DDR SDRAM controller bus interface Xilinx, Inc.
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0OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller (v2.00b) DS424 March 1, 200600Product Specification DS424 Mar

Specifications	DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller PLB DDR SDRAM controller bus interface Xilinx, Inc.
Outline	OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller (v2.00b) Introduction Features OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters Allowable Parameter Combinations OPB DDR SDRAM Controller Design Parameters OPB DDR SDRAM Controller I/O Signals Parameter-Port Dependencies Connecting to Memory OPB DDR SDRAM Controller Design DDR Clocking Timing Diagrams Design Constraints Design Implementation Reference Documents Revision History
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Content	0OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller (v2.00b) DS424 March 1, 200600Product Specification DS424 March 1, 2006www.xilinx.com1 Product Specification © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this fea- ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran- ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The Xilinx On-chip Peripheral Bus Double Data Rate (OPB DDR) Synchronous DRAM (SDRAM) controller that connects to the OPB and provides the control interface for DDR SDRAMs. It is assumed that the reader is familiar with DDR SDRAMs and the IBM PowerPC™. Features The Xilinx OPB DDR SDRAM Controller is a soft IP core designed for Xilinx FPGAs and contains the following features: •OPB interface •Performs device initialization sequence upon power-up and reset conditions for ~200uS. Provides a parameter to adjust this time for simulation purposes only •Performs auto-refresh cycles •Supports CAS latencies of 2 or 3 set by a design parameter •Supports 16, 32 and 64 bits DDR data widths set by a design parameter •Supports indeterminate burst length •Provides big-endian connections to memory devices, See Connecting to Memory for details on memory connections •Supports multiple (up to 4) DDR memory banks •Supports capability to separate DDR clock frequency from OPB clock frequency for the tested values shown in Table 12 and simulated values shown in Table 13. LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Virtex-II, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-3, Spartan-3E Version of Coreopb_ddrv2.00b Resources Used. See Table 13 MinMax Slices3731238 LUTs3961412 FFs3741225 Block RAMsN/AN/A Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsNone Design Tool Requirements Xilinx Implementation ToolsISE 6.2i or later VerificationN/A SimulationModelSim SE/EE 5.8b or later SynthesisXST 6.2i later Support Support provided by Xilinx, Inc. Discontinued IP
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Following Datasheets	opb_deltasigma_adc (13 pages) opb_deltasigma_dac (19 pages) opb_device_bfm (2 pages) opb_emc (34 pages) opb_epc (45 pages) opb_ethernet (54 pages) opb_ethernetlite (23 pages) opb_hwicap (7 pages) opb_iic (20 pages) opb_intc (21 pages)
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DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller PLB DDR SDRAM controller bus interface Xilinx, Inc.

DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller DS425 PLB Double Data Rate \DDR\ Synchronous DRAM \SDRAM\ Controller PLB DDR SDRAM controller bus interface Xilinx, Inc.