OPB Central DMA OPB Central DMA OPB Central DMA Xilinx, Inc.

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Specifications	OPB Central DMA OPB Central DMA OPB Central DMA Xilinx, Inc.
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0 OPB Central DMA Controller DS472 December 1, 200500Product Specification DS472 December 1, 2005www.xilinx.com1 Product Spec

Specifications	OPB Central DMA OPB Central DMA OPB Central DMA Xilinx, Inc.
Outline	OPB Central DMA Controller Introduction Features DMA Operation Operation from the OPB Viewpoint Burst Behavior OPB Central DMA Controller Register Descriptions Software Reset Register (RST) Module Identification Register (MIR DMA Control Register (DMACR) Source Address Register (SA) Destination Address Register (DA) Length Register (LENGTH) DMA Status Register (DMASR) Interrupt Status Register (ISR) Interrupt Enable Register (IER)
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Content	0 OPB Central DMA Controller DS472 December 1, 200500Product Specification DS472 December 1, 2005www.xilinx.com1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The OPB Central DMA Controller provides simple Direct Memory Access (DMA) services for peripherals and mem- ory devices on the OPB bus. The controller moves a pro- grammable quantity of data from a source address to a destination address without processor intervention. Features •Provides a single physical channel of Direct Memory Access between a source address and a destination address •Provides programmable registers for transfer length, source address, destination address, and dataword size •Byte, halfword, and word data sizes supported •Supports keyhole addressing (word data size, only) •Provides fast internal data buffer to support OPB burst transfers LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-E Version of Coreopb_central_dmav1.00c Resources Used MinMax Slices187215 LUTs307357 FFs271282 Block RAMs00 Provided with Core DocumentationProduct Specification Design File FormatsN/A Constraints FileN/A VerificationN/A Instantiation Template N/A Reference DesignsN/A Design Tool Requirements Xilinx Implementation Tools N/A VerificationN/A SimulationN/A Discontinued IP
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Following Datasheets	opb_ddr (50 pages) opb_deltasigma_adc (13 pages) opb_deltasigma_dac (19 pages) opb_device_bfm (2 pages) opb_emc (34 pages) opb_epc (45 pages) opb_ethernet (54 pages) opb_ethernetlite (23 pages) opb_hwicap (7 pages) opb_iic (20 pages)
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