Product Specification DS469 OPB Arbiter OPB,arbiter,bus,FPGA,interface,slave,master,priority,Virtex,

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Specifications	Product Specification DS469 OPB Arbiter OPB,arbiter,bus,FPGA,interface,slave,master,priority,Virtex,Spartan,QPro Xilinx, Inc.
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0 OPB Arbiter (v1.02e) DS469 September 23, 200500Product Specification DS469 September 23, 2005www.xilinx.com1 Product Specif

Specifications	Product Specification DS469 OPB Arbiter OPB,arbiter,bus,FPGA,interface,slave,master,priority,Virtex,Spartan,QPro Xilinx, Inc.
Outline	OPB Arbiter (v1.02e) Introduction Features Functional Description OPB Slave Interface (IPIF) Control Register Logic Priority Register Logic Priority Register Update Logic Priority Registers and Register Update Logic Block Diagram ARB2BUS Data Mux Arbitration Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Grant Last Register Lock Logic Park Logic Grant Logic Park/Lock Logic Watchdog Timer Design Implementation Specification Exceptions Reference Documents Revision History
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Content	0 OPB Arbiter (v1.02e) DS469 September 23, 200500Product Specification DS469 September 23, 2005www.xilinx.com1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The On-Chip Peripheral Bus (OPB) Arbiter design described in this document incorporates the features contained in the IBM On-chip Peripheral Bus Arbiter Core manual (version 1.5) for 32-bit implementation, which is referenced throughout this document and is considered the authoritative specification. Any differences between the IBM OPB Arbiter implementation and the Xilinx OPB Arbiter implementation are explained in the Specification Exceptions section of this document. The Xilinx OPB Arbiter design allows the user to tailor the OPB Arbiter to suit a specific application by setting certain parameters to enable/disable features. In some cases, setting these parameters may cause the Xilinx OPB Arbiter design to deviate slightly from the IBM OPB Arbiter specification. These parameters are described in the OPB Arbiter Design Parameters section of this document. Features •The OPB Arbiter is a soft IP core designed for Xilinx FPGAs and contains the following features: •Optional OPB slave interface (included in design via a design parameter) •OPB Arbitration -arbitrates between 1–16 OPB Masters (the number of masters is parameterizable) -arbitration priorities among masters programmable via register write -priority arbitration mode configurable via a design parameter ·Fixed priority arbitration with processor access to read/write Priority Registers ·Dynamic priority arbitration implementing a true least recent used (LRU) algorithm LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Virtex, Virtex-II, Virtex-E, Virtex-II Pro, Virtex-4 Version of Coreopb_arbiterv1.02e Resources Used MinMax I/O4904 LUTs6252 FFs41477 Block RAMs00 Provided with Core DocumentationProduct Specification Design File FormatsVHDL Constraints FileN/A VerificationN/A Instantiation TemplateN/A Reference DesignsNone Design Tool Requirements Xilinx Implementation Tools5.1i or later VerificationN/A SimulationModelSim SE/EE 5.6e or later SynthesisXST Support Support provided by Xilinx, Inc. Discontinued IP
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Following Datasheets	opb_atmc (24 pages) opb_bram_if_cntlr (9 pages) opb_central_dma (12 pages) opb_ddr (50 pages) opb_deltasigma_adc (13 pages) opb_deltasigma_dac (19 pages) opb_device_bfm (2 pages) opb_emc (34 pages) opb_epc (45 pages) opb_ethernet (54 pages)
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Product Specification DS469 OPB Arbiter OPB,arbiter,bus,FPGA,interface,slave,master,priority,Virtex,Spartan,QPro Xilinx, Inc.

Product Specification DS469 OPB Arbiter OPB,arbiter,bus,FPGA,interface,slave,master,priority,Virtex,Spartan,QPro Xilinx, Inc.