
| Specifications | |
| Business section |

| Specifications | |
| Outline | ORDERING INFORMATION |
| Suggested Link Details/Purchase | |
| Content | PI7C8150A 2-PORT PCI-to-PCI BRIDGE DATA BRIEF PERICOM SEMICONDUCTOR CORPORATION 2380 Bering Drive • San Jose, CA 95131 • (800) 435-0800 • Fax (408) 435-1100 • http://www.pericom.com 10/10/2003, REVISION 1.0 Page 1 PI7C8150A: 32-bit 2-Port PCI-to-PCI Bridge PRODUCT FEATURES • 32-bit / 66MHz primary and secondary ports • Compliant with the following specifications: − PCI Local Bus Specification, Revision 2.2 − PCI-to-PCI Bridge Architecture Specification, Revision 1.1 − Advanced Configuration Power Interface (ACPI) Specification − PCI Power Management Specification, Revision 1.0 • Concurrent primary and secondary port operation • Provides internal arbitration for one set of 9 secondary bus masters − Programmable 2-level priority arbiter − Disable control to allow use of an external arbiter • Supports posted write buffers in both directions (downstream and upstream) • Two 128-byte FIFO’s for delay transactions • Two 128-byte FIFO’s for posted memory transactions • Enhanced address decoding − 32-bit I/O address range − 32-bit memory-mapped I/O address range − VGA addressing and VGA palette snooping − ISA-aware mode for legacy support in the first 64KB of I/O address range • IEEE 1149.1 JTAG interface support • 3.3V core; 3.3V and 5V PCI I/O interface • Packages − 208-pin QFP − 256-pin PBGA • Available in 66MHz and 33MHz • Intel 21150 compatible PRODUCT DESCRIPTION The PI7C8150A is a 2-port PCI-to-PCI Bridge designed to be fully compliant with the PCI Local Bus Specification, Revision 2.2. Both the primary and secondary ports are specified to run at 32-bit and up to 66MHz. The PI7C8150A supports synchronous bus transactions between devices on the primary bus and the secondary bus. The two buses can operate in concurrent mode, resulting in added increase in system performance. Concurrent bus operation off-loads and isolates traffic on a single bus by allowing a master and target on the same bus to communicate with each other while the other bus is busy. The PCI Local Bus Specification denotes loading restrictions on the PCI bus. The PI7C8150A allows designers to expand the loading capability by adding a second PCI bus. On motherboards, more PCI slots or devices can then be added on this second PCI bus. On add-in cards, more than one device can now reside on the add-in card (PCI Local Bus Specifications specify that each add-in card may only have one device because there may only be one connection per PCI signal in the add-in card connector). ORDERING INFORMATION PART NUMBER SPEED PACKAGE PI7C8150AMA 66 MHz 208-FQFP PI7C8150AMA-33 33 MHz 208-FQFP PI7C8150AND 66 MHz 256-PBGA PI7C8150AND-33 33 MHz 256-PBGA |
| Navigation | Previous Page / Next Page |
| Following Datasheets | PI7C8150B_db_2 (2 pages) PI7C9X440SL_db_3 (1 pages) PI7C9X442SL_db_3 (1 pages) PID_C_1 (14 pages) PID_CR_1 (6 pages) PID_HMCR_1 (2 pages) PID_HQN_1 (2 pages) PID_HVC_1 (2 pages) PID_LIC_1 (4 pages) PID_LMCI_1 (5 pages) |
Check in e-portals![]() |
World-H-News Products Extensions Partners Automation Jet Parts |
| Sitemap Folder | group1 group2 group3 group4 group5 group6 group7 group8 group9 group10 group11 group12 group13 group14 group15 group16 group17 group18 group19 group20 group21 group22 group23 group24 group25 group26 group27 group28 group29 group30 group31 group32 group33 group34 group35 group36 group37 group38 group39 group40 group41 group42 group43 group44 group45 group46 group47 group48 group49 group50 group51 group52 group53 group54 group55 group56 group57 group58 group59 group60 group61 group62 group63 group64 group65 group66 group67 group68 group69 group70 group71 group72 group73 group74 group75 group76 group77 group78 group79 group80 group81 group82 group83 group84 group85 group86 group87 group88 group89 group90 group91 group92 group93 group94 group95 group96 group97 group98 group99 group100 Prewious Folder Next Folder |