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1PI6CX201A Rev. C 01/03/2012 Block Diagram PI6CX201A 25MHz Jitter Attenuator Features • PLL with quartz stabilized VCXO

Specifications
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Content	1PI6CX201A Rev. C 01/03/2012 Block Diagram PI6CX201A 25MHz Jitter Attenuator Features • PLL with quartz stabilized VCXO • Optimized for 25MHz input/output frequency • Other frequencies available • Low phase jitter less than 350fs typical • Free run mode ±100ppm • Single ended input and outputs • 3.3V single supply • Lock detection • Industrial Temperature: –40°C to 85°C • 20-pin TSSOP package Description The PI6CX201A is composed of a phase-locked loop with integrated VCXO oscillator for use in the clock jitter attenuation applications. It is optimized for use with a SaRonix-eCera™ crystal of 25MHz, and has typical output phase jitter less than 350fs (RMS). Pin Conﬁguration X11 LF 2 AGND3 S0 4 VC 5 6 7 8FREE_RUN S1 S2 X220 DGND 19 CLK_OUT1 18 17 AVDD 16 15 14 13 DVDD LD CLK_OUT2 DGND 9 10DVDD DGND12 11 FB_CLK REF_CLK PFD Pre DividerREF_CLK S0 S1 Charge PumpVCXO Divider Lock Detector S0 S1 LF VC LD CLK_OUT1 CLK_OUT2 FB_CLK S2 S2 SaRonix-eCera xtal External Free_Run External Connection Required 12-0150
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Following Datasheets	PI6PCIEB24_2 (7 pages) PI6UMC10802_2 (5 pages) PI7C8150A_db_2 (2 pages) PI7C8150B_db_2 (2 pages) PI7C9X440SL_db_3 (1 pages) PI7C9X442SL_db_3 (1 pages) PID_C_1 (14 pages) PID_CR_1 (6 pages) PID_HMCR_1 (2 pages) PID_HQN_1 (2 pages)
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