PI6C2510-133E.indd JTHo

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Specifications	PI6C2510-133E.indd JTHo
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1PS8505B 11/18/09 Block Diagram PI6C2510-133E Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs Features •

Specifications	PI6C2510-133E.indd JTHo
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Content	1PS8505B 11/18/09 Block Diagram PI6C2510-133E Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs Features • Operating Frequency up to 150 MHz • Low-Noise Phase-Locked Loop Clock Distribution that meets 133 MHz Registered DIMM Synchronous DRAM modules for server/workstation/PC applications • Allows Clock Input to have Spread Spectrum modulation for EMI reduction • Low jitter: Cycle-to-Cycle jitter ±75ps max. • On-chip series damping resistor at clock output drivers for low noise and EMI reduction • Operates at 3.3V VCC, 0–85°C • Packages (Pb-free & Green available): – Plastic 24-pin TSSOP (L) Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing one clock input to one bank of ten outputs, with an output enable. This clock driver is designed to meet the PC133 SDRAM Registered DIMM speciﬁ cation. For test purposes, the PLL can be bypassed by strapping AVCC to ground. Pin Conﬁ guration G 10 CLK_IN FB_IN PLL AVcc FB_OUT Y[0:9] 24-Pin L AGND VCCY0 Y1 Y2 GND GND Y3 Y4 VCCG FB_OUT CLK_IN AVCCVCCY9 Y8 GND GND Y7 Y6 Y5 VCCFB_IN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Functional Table InputsOutputs GY[0:9]FB_OUT LLCLK_IN HCLK_INCLK_IN 09-0006
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