| Specifications | PI6CE855 PLL clock device is developed for SSTE DDR3 Memory Applications Pericom Product Datasheet - PLL Clock Driver for 1.35V/1.5V SSTE DDR3 Memory Kay Annamalai |
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| Specifications | PI6CE855 PLL clock device is developed for SSTE DDR3 Memory Applications Pericom Product Datasheet - PLL Clock Driver for 1.35V/1.5V SSTE DDR3 Memory Kay Annamalai |
| Business section |

| Specifications | PI6CE855 PLL clock device is developed for SSTE DDR3 Memory Applications Pericom Product Datasheet - PLL Clock Driver for 1.35V/1.5V SSTE DDR3 Memory Kay Annamalai |
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| Content | 1www.pericom.com P-0.1 04/27/11 PI6C20800B Block Diagram Pin Configuration (48-Pin TSSOP) Description PI6C20800B is a PCIe 3.0 compliant, high-speed, low-noise differential clock buffer designed to be a companion to PCI Express 3.0 clock generator for Intel server chipsets. The device distributes the differential SRC clock from PCIe clock generator to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated. Features Î Phase jitter filter for PCIe 3.0 application Î Eight Pairs of Differential Clocks Î Low skew < 50ps (PI6C20800B), <60ps (PI6C20800BI) Î Low Cycle-to-cycle jitter < 60ps Î Output Enable for all outputs Î Outputs Tristate control via SMBus Î Power Management Control Î Programmable PLL Bandwidth Î PLL or Fanout operation Î 3.3V Operation Î Industrial Temperature Option - PI6C20800BI Î Packaging (Pb-Free & Green): — 48-Pin TSSOP (A) PCI Express® 3.0 1:8 HCSL Clock Buffer OUT0OUT0# OUT1OUT1# OUT2OUT2# OUT3OUT3# DIV OutputControl SMBusController PLLPLL_BW# SRCSRC# PLL/BYPASS# SRC_DIV# SCLKSDA OE_INVOE [0:7]SRC_STOP#PWRDWN# OUT4OUT4# OUT5OUT5# OUT6OUT6# OUT7OUT7# LOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_A VSS_A IREF LOCK OE_7 OE_4 OUT7 OUT7# OE_INV VDD OUT6 OUT6# OE_6 OE_5 OUT5 OUT5# VSS VDD OUT4 OUT4# PLL_BW# SRC_STOP# PWRDWN# VSS SRC_DIV# VDD VSS SRC SRC# OE_0 OE_3 OUT0 OUT0# VSS VDD OUT1 OUT1# OE_1 OE_2 OUT2 OUT2# VSS VDD OUT3 OUT3# PLL/BYPASS# SCLK SDA 11-0049 |
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| Following Datasheets | PI6C20800S_3 (10 pages) PI6C22405-1H_2 (6 pages) PI6C22405_2 (6 pages) PI6C22409-1H_2 (7 pages) PI6C22409_2 (7 pages) PI6C22510_2 (6 pages) PI6C2409-1H_2 (8 pages) PI6C2410_2 (6 pages) PI6C2504A_2 (4 pages) PI6C2509-133_2 (5 pages) |
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