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| Content | is mounted on the PCB. The passivation layer also protects the termination and gate structures from moisture and other contamination. The copper can forms the drain connection from the other side of the die to the board. This design eliminates the lead- frame and wire bonds, reducing die-free package resistance (DFPR) to a mere 0.1mOhm in an SO-8 footprint compared to 1.5 mOhm for the standard SO- 8 package. The large-area contacts combined with the copper housing significantly improve heat dissipation compared to a SOIC plastic molded package: the junction-to-PCB thermal resistance is reduced to 1°C/W, compared to 20°C/W for a standard SO-8 package. The copper ‘can’ provides a heat sink surface, improving top junction-to-case thermal resistance to 3°C/W compared to 18°C/W for a SO-8. With the use of heatsinks and cooling air flow, the DirectFET package can dissipate more heat out of the top of the package, reducing junction temperature by up to 50°C compared to the SO-8 solution. Effective top-side cooling means that heat dissipated can be pulled away from the circuit board, increasing the currents that the device can safely carry. High top Rth(J-C) explains why standard and derivative SO-8 packages are only used with single-side cooling through the PCB. III. VRM DESIGN USING DIRECTFET MOSFETS To demonstrate the benefits of this new packaging technology in a VRM design, a high current 4-phase VRM was designed using DirectFET MOSFETs. The board is a 6-layer PCB using 4oz. Copper/layer. The 4-phase controller and the drivers used in the design are capable of operating at up to 2MHz/phase. To enable a small solution footprint, ceramic capacitors were used for both the input and output filter while the inductor is a 400nH high-current, small footprint coil (10mmX10mm). The low profile of the DirectFET MOSFETs allows the converter design to be configured with the devices on the back of the board and a heat sink to be mounted on top of them while still staying within VRM 9.1 outline specifications. The heat sink is an aluminum finned heat sink measuring in 3.75in x 0.75in. It was attached on top of the DirectFET MOSFETs using an electrically isolating, heat conducting epoxy. A single high side (IRF6604) and a single low side (IRF6607) DirectFET MOSFET are utilized per phase. To improve efficiency a chip scale packaged Scottky diode (IR140CSP) was used in parallel with the synchronous FET. The low inductance of the DirectFET package and the chip scale packaged Scottky diode minimizes loop inductance and thus reduces body diode losses during MOSFET dead time. The design is capable of 120A (30A/phase) at high efficiency in a 3.8in x 1.1in footprint at room temperature and with 600LFM airflow. The specifications of the 30V DirectFET control and synchronous FET are shown in TABLE I. Note the high current capability (ID) of both the devices which eliminates the need to parallel devices. Figure 2. Images of front and rear sides of the 4- phase VRM board with DirectFET MOSFETs shown mounted on the rear side. The heat sink is not shown. TABLE I: SPECIFICATIONS Note: All values typical ??TCASE = 25?C In-circuit efficiency measurements were made on the module at 500kHz using 600LFM airflow at room ambient. The module achieved 82% efficiency at 120A full load as shown in Figure 3. It is important to optimize gate drive voltage according to the frequency of operation. As can be seen in this case, a gate drive voltage of 7.5VGS for 500kHz operation offers better efficiency at higher load currents than the 5VGS gate drive. Part # RDS(on) mOhm @10VGS QG (nC) QGD (nC) QGS (nC) ID (A) IRF6607 2.5 50 16 17 94* IRF6604 9 17 6.3 5.1 49* |
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| Following Datasheets | pci_32_ds206_1 (13 pages) pci_64_ds205_1 (12 pages) PCN-1026_2 (1 pages) PCN-1027_2 (1 pages) PCN-1042_2 (2 pages) PCN-1084_2 (2 pages) PCN-2003-1028_2 (1 pages) PCN-2003-1029_2 (1 pages) pcn0005_1 (1 pages) pcn0404_2 (1 pages) |
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