The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI com

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Specifications	The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.
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DS205 March 9, 2012www.xilinx.com2 ProductSpecification v3.167 & v4.16 LogiCORE IP 64-Bit Initiator/Target v3 & v4 fo

Specifications	The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.
Outline	LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI Features Applications General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Functional Description Core Configuration Burst Transfer Supported PCI Commands Bandwidth Recommended Design Experience Timing Specifications Support Ordering Information Revision History Notice of Disclaimer
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Content	DS205 March 9, 2012www.xilinx.com2 ProductSpecification v3.167 & v4.16 LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI Xilinx provides technical support for this LogiCORE IP product when used as described. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if customized beyond that described in the related product documentation. For Spartan®-6 devices, only those devices listed in Table1 have been tested with the latest software speed files to meet PCI timing. For a part or package not listed in the data sheet, open a WebCase with Xilinx for latest available status. Table 1:Core Implementation Supported Device(1),(2)Core VersionSignaling Environment 64/66 Core Virtex-5 XC5VFX70T-FF1136-2C/I(3) (regional clock)v43.3V only Virtex-5 XC5VLX50-FF1153-2C/I(3) (regional clock)v43.3V only Virtex-5 XC5VLX50T-FF1136-2C/I(3) (regional clock)v43.3V only Virtex-5 XC5VLX110-FF1153-2C/I(3) (regional clock)v43.3V only Virtex-5 XC5VLX110T-FF1136-2C/I(3) (regional clock)v43.3V only Virtex-5 XC5VSX50T-FF1136-2C/I(3) (regional clock)v43.3V only Virtex-5 XC5VSX95T-FF1136-2C/I(3) (regional clock)v43.3V only Virtex-4 XC4VFX20-FF672-11C/I(3) (regional clock)v33.3V only Virtex-4 XC4VLX25-FF668-11C/I(3),(4) (regional clock)v33.3V only Virtex-4 XC4VSX35-FF668-11C/I(3),(4) (regional clock)v33.3V only Spartan-3A XC3S400A-FG400-5Cv33.3V only Spartan-3A XC3S700A-FG400-5Cv33.3V only Spartan-3A XC3S700A-FG484-5Cv33.3V only Spartan-3A XC3S1400A-FG484-5Cv33.3V only Spartan-3A XC3S1400A-FG676-5Cv33.3V only Spartan-3ADSP XC3SD1800A-FG676-5Cv33.3V only Spartan-3ADSP XC3SD3400A-FG676-5Cv33.3V only Spartan-3E XC3S1200E-FG400-5C(4) v33.3V only 64/33 Core Kintex™-7 XC7K70T-SBG324-1C/Iv43.3V only Kintex-7 XC7K70T-FBG484-1C/Iv43.3V only Kintex-7 XC7K70T-FBG676-1C/Iv43.3V only Kintex-7 XC7K160T-FBG484-1C/Iv43.3V only Kintex-7 XC7K160T-FBG676-1C/Iv43.3V only Kintex-7 XC7K160T-FFG676-1C/Iv43.3V only Kintex-7 XC7K325T-FBG676-1C/Iv43.3V only Kintex-7 XC7K325T-FBG900-1C/Iv43.3V only Kintex-7 XC7K325T-FFG676-1C/Iv43.3V only Kintex-7 XC7K325T-FFG900-1C/Iv43.3V only Kintex-7 XC7K355T-FFG901-1C/Iv43.3V only Kintex-7 XC7K410T-FBG676-1C/Iv43.3V only Kintex-7 XC7K410T-FBG900-1C/Iv43.3V only
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Following Datasheets	PCN-1026_2 (1 pages) PCN-1027_2 (1 pages) PCN-1042_2 (2 pages) PCN-1084_2 (2 pages) PCN-2003-1028_2 (1 pages) PCN-2003-1029_2 (1 pages) pcn0005_1 (1 pages) pcn0404_2 (1 pages) pcn0407_1 (1 pages) PCN0813_FP-146_Amendment1-1_1 (4 pages)
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The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.

The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.