ProASIC3/E Production FPGAs

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Specifications	ProASIC3/E Production FPGAs
Business section

Table of Contents 2ProASIC3/E Production FPGAs Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specifications	ProASIC3/E Production FPGAs
Outline	Introduction Figure 1: ProASIC3 - Best of Both ASIC and SRAM FPGA Worlds Product Features VersaTile User Nonvolatile Memory (NVM) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Figure 4: Clock Conditioning Circuitry (Not all CCCs contain a PLL) SRAM and FIFO Clock Conditioning Circuitry (CCC) and PLLs Global Clocking I/O Structure UJTAG Hot-Swap Support Security Firm-Error Immunity Power Management
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Content	Table of Contents 2ProASIC3/E Production FPGAs Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Cost-Optimized Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VersaTile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 User Nonvolatile Memory (NVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM and FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Clock Conditioning Circuitry (CCC) and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Global Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 UJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hot-Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Firm-Error Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FlashPoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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