ACT-Q109_PA3-PIB_Feb09_v1.qxd Andrew Fukutome

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Specifications	ACT-Q109_PA3-PIB_Feb09_v1.qxd Andrew Fukutome
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Flash FPGAsActel ProASIC3 Family Product Table EXOS Ebisu Building 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150, Japan Phone +81.03.

Specifications	ACT-Q109_PA3-PIB_Feb09_v1.qxd Andrew Fukutome
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Content	Flash FPGAsActel ProASIC3 Family Product Table EXOS Ebisu Building 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150, Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Actel Japan River Court, Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 Actel Europe Ltd. 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Corporation Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn Actel Hong Kong www.actel.com © 2009 Actel Corporation. All rights reserved. The Actel name and logo are trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. 55700003-16/2.09 For more information regarding ProASIC3 Flash FPGA families, please visit the Actel website at www.actel.comor contact your local sales representative. Printed on recycled paper ProASIC3 DevicesA3PN010A3PN015A3P015A3PN020A3PN030A3P030A3PN060A3P060A3PN125A3P125 System Gates10 k15 k15 k20 k30 k30 k60 k60 k125 k125 k Typ. Equivalent Macrocells861281281752562565125121,0241,024 VersaTiles (D-flip-flops)2603843845207687681,5361,5363,0723,072 RAM kbits (1,024 bits)––––––18183636 4,608-Bit Blocks––––––4488 FlashROM (bits)1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k Secure (AES) ISP3––––––YesYesYesYes Integrated PLL in CCCs––––––1111 VersaNet Globals144646618181818 I/O StandardsStd., Std., Std., Std., Std.,Std., Std., Std.+Std., Std.+ Hot-SwapHot-SwapHot-SwapHot-SwapHot-SwapHot-SwapHot-SwapHot-Swap I/O Banks (+ JTAG)2323222222 Speed GradesStd., -1, -2Std., -1, -2-F, Std., -1, -2Std., -1, -2Std., -1, -2-F, Std., -1, -2Std., -1, -2-F, Std., -1, -2Std., -1, -2-F, Std., -1, -2 Temperature GradesC, IC, IC, IC, IC, IC, IC, IC, IC, IC, I Package PinsQN48QN68QN68QN68QN48QN48VQ100QN132VQ100QN132 QN68QN68VQ100VQ100 VQ100QN132TQ144TQ144 VQ100FG144PQ208 FG144 Notes:1Six chip (main) and twelve quadrant global networks are available for PA3060 and above. 2Device/package support TBD. 3AES not available for ARM-enabled ProASIC3 devices. 4The M1A3P250 device does not support this package. ProASIC3 DevicesA3PN250A3P250LA3P250A3P400A3P600A3PE600A3P600LA3P1000A3P1000LA3PE1500A3PE3000A3P3000L ARM-Enabled ARM7M7A3P1000 ProASIC3 Devices ARM-Enabled Cortex-M1M1A3P250M1A3P400M1A3P600M1A3P600LM1A3P1000M1A3P1000LM1A3PE1500M1A3P3000M1A3P3000L ProASIC3 Devices System Gates250 k250 k250 k400 k600 k600 k600 k1 M1 M1.5 M3 M3 M VersaTiles (D-flip-flops)6,1446,1446,1449,21613,82413,82413,82424,57624,57638,40075,26475,264 RAM kbits (1,024 bits)36363654108108108144144270504504 4,608-Bit Blocks88812242424323260112112 FlashROM (bits)1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k Secure (AES) ISP3YesYesYesYesYesYesYesYesYesYesYesYes Integrated PLL in CCCs111116111666 VersaNet Globals1181818181818181818181818 I/O StandardsStd.,Hot-SwapStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDSStd.+/ LVDS I/O Banks (+ JTAG)444448444888 Speed GradesStd.,-1,-2-F,Std.,-1-F,Std.,-1,-2-F,Std.,-1,-2-F,Std.,-1,-2-F,Std.,-1,-2-F,Std.,-1-F,Std.,-1,-2-F,Std.,-1-F,Std.,-1,-2-F,Std.,-1,-2-F,Std.,-1 Temperature GradesC, IC, IC, IC, IC, IC, IC, IC, IC, IC, IC, IC, I Package PinsVQ100VQ100QN132FG144FG144PQ208PQ208FG144PQ208PQ208PQ208PQ208 PQ208VQ100FG256FG256FG256FG144FG256FG144FG484FG324FG324 FG144FG144FG484FG484FG484FG256FG484FG256FG676FG484FG484 FG256FG256FG484FG484FG896FG896
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Following Datasheets	PA3_E_Tech_WP_1 (18 pages) pabp_01 (5 pages) pabp_02 (7 pages) package_diode_5 (5 pages) packaging_auto_1 (18 pages) PAH_Free_Conformance-1_2 (1 pages) pajp_01 (5 pages) pajp_02 (5 pages) ParkGroup (4 pages) pbga-400ld_1 (1 pages)
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