The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI com

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Specifications	The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.
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DS205 March 9, 2012www.xilinx.com1 ProductSpecification v3.167 & v4.16 © Copyright 2010–2012 Xilinx, Inc. Xili

Specifications	The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.
Outline	LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI Features Applications General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Smart-IP Technology General Description Functional Description Core Configuration Burst Transfer Supported PCI Commands Bandwidth Recommended Design Experience Timing Specifications Support Ordering Information Revision History Notice of Disclaimer
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Content	DS205 March 9, 2012www.xilinx.com1 ProductSpecification v3.167 & v4.16 © Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIExpress, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. Features •Fully compliant 64-bit, 66/33 MHz LogiCORE™ IP Initiator/Target core for PCI™ •Customizable, programmable, single-chip solution •Pre-defined implementation for predictable timing •Incorporates Xilinx Smart-IP technology •3.3V operation at 0–66 MHz •5.0V operation at 0–33 MHz •Fully verified design tested with Xilinx proprietary test bench and hardware •Delivered through Xilinx® CORE Generator™ software •CardBus compliant •Supported initiator functions: •Configuration read, configuration write •Memory read, memory write, MRM, MRL •Interrupt acknowledge, special cycles •I/O read, I/O write •Supported target functions: •Type 0 configuration space header •Up to three base address registers (MEM or I/O with adjustable block size from 16 bytes to 2 GB) •Medium decode speed •Parity generation, parity error detection •Configuration read, configuration write •Memory read, memory write, MRM, MRL •Interrupt acknowledge •I/O read, I/O write •Target abort, target retry, target disconnect LogiCORE IP 64-BitInitiator/Target v3 & v4 for PCI DS205 March 9, 2012ProductSpecification v3.167 & v4.16 LogiCORE IP Facts Core Specifics Supported Device Family(1) 1.For a complete listing of supported devices, see the release notes for this core. See Table1. Resource Utilization(2) 2.Resource utilization depends on core configuration and design requirements. Unused resources are trimmed by the Xilinx technology mapper. Utilization figures reported represent a maximum configuration. v4 Core v3 Core LUTs565724 Slice Flip-Flops404732 IOB Flip-Flops94176 IOBs9489 GCLK(3) 3.Designs running at 66 MHz in Virtex®-4 and Virtex-5 FPGA imple- mentations require additional BUFG for 200 MHz reference clock. 2 1 Provided with Core Documentation Product Specification v3 & v4 Getting Started Guide v3 User Guide v4 User Guide v3 Design File Formats VHDL/Verilog Simulation Model NGC Netlist (v4 core only) NGO Netlist (v3 core only) Constraints FileUser Constraints File (UCF) Test BenchVHDL/Verilog Example Test Bench Instantiation TemplateVHDL/Verilog Wrapper Example DesignsVHDL/Verilog Example Design Design Tool Requirements Xilinx Implementation ToolsISE® 13.4 Simulation(4) 4.For the supported versions of the tools, see the ISE Design Suite 13: Release Notes Guide. Mentor Graphics ModelSim Cadence Incisive Enterprise Simulator (IES) SynthesisXilinx XST Support Provided by Xilinx @ www.xilinx.com/support
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Following Datasheets	PCN-1026_2 (1 pages) PCN-1027_2 (1 pages) PCN-1042_2 (2 pages) PCN-1084_2 (2 pages) PCN-2003-1028_2 (1 pages) PCN-2003-1029_2 (1 pages) pcn0005_1 (1 pages) pcn0404_2 (1 pages) pcn0407_1 (1 pages) PCN0813_FP-146_Amendment1-1_1 (4 pages)
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The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.

The 64-Bit Initiator/Target v3 and v4 for PCI core provides an interface for users to design PCI comp\ liant solutions. Xilinx DS205 64-Bit Initiator/Target v3 & v4 for PCI, Data Sheet PCI,PCI64,PCI64 Interface,initiator, target, ds205, 64-bit Xilinx, Inc.