This data sheet outlines the LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, which is a ful

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Specifications	This data sheet outlines the LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, which is a fully co\ mpliant, customizable single-chip solution. Xilinx DS206 LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, Data Sheet ds206, pci, 32-bit, intiator, target Xilinx, Inc.
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DS206 March 9, 2012www.xilinx.com1 ProductSpecification v3.167 & v4.16 © Copyright 2010–2012 Xilinx, Inc. Xili

Specifications	This data sheet outlines the LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, which is a fully co\ mpliant, customizable single-chip solution. Xilinx DS206 LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, Data Sheet ds206, pci, 32-bit, intiator, target Xilinx, Inc.
Outline	LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI Features Applications General Description Smart-IP Technology Functional Description I/O Interface Block User Application Configuration Space Parity Generator/Checker Initiator State Machine Target State Machine Supported Commands for PCI Bandwidth Recommended Design Experience Timing Specifications Support Ordering Information Revision History Notice of Disclaimer
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Content	DS206 March 9, 2012www.xilinx.com1 ProductSpecification v3.167 & v4.16 © Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIExpress, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. Features •Fully compatible 32-bit, 66/33 MHz Initiator/Target core for PCI™ •Customizable, programmable, single-chip solution •Pre-defined implementation for predictable timing •Incorporates Xilinx Smart-IP technology •3.3V operation at 0–66 MHz •Fully verified design tested with Xilinx proprietary test bench and hardware •Delivered through the Xilinx® CORE Generator™ software •CardBus compliant •Supported initiator functions: •Configuration read, configuration write •Memory read, memory write, MRM, MRL •Interrupt acknowledge, special cycles •I/O read, I/O write •Supported target functions: •Type 0 configuration space header •Up to three base address registers (MEM or I/O with adjustable block size from 16 bytes to 2 GB) •Medium decode speed •Parity generation, parity error detection •Configuration read, configuration write •Memory read, memory write, MRM, MRL •Interrupt acknowledge •I/O read, I/O write •Target abort, target retry, target disconnect LogiCORE IP 32-BitInitiator/Targetv3 & v4 for PCI DS206 March 9, 2012ProductSpecification v3.167 & v4.16 LogiCORE IP Facts Table Core Specifics Supported Device Family(1) 1.For a complete listing of supported devices, see the release notes for this core. See Table1. Resources Used(2) 2.Depends on configuration of the interface and design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported represent a maximum configuration. v4 Corev3 Core LUTs506553 Slice Flip-Flops333566 IOB Flip-Flops27097 IOBs5550 GCLKs(3) 3.Virtex®-4 and Virtex-5 FPGA implementations require additional BUFG for 200 MHz reference clock. 21 Provided with Core Documentation Product Specification v3 & v4 Getting Started Guide v3 User Guide v4 User Guide v3 Design File Formats VHDL/Verilog Simulation Model NGC Netlist (v4 core only) NGO Netlist (v3 core only) Constraints FileUser Constraints File (UCF) Test BenchVHDL/Verilog Example Test Bench Instantiation TemplateVHDL/Verilog Wrapper Example DesignVHDL/Verilog Example Design Design Tool Requirements Xilinx Implementation ToolsISE® v13.4 Simulation(4) 4.For the supported versions of the tools, see the ISE Design Suite 13: Release Notes Guide. Mentor Graphics ModelSim Cadence Incisive Enterprise Simulator (IES) SynthesisXilinx XST Support Provided by Xilinx @ www.xilinx.com/support
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Following Datasheets	pci_64_ds205_1 (12 pages) PCN-1026_2 (1 pages) PCN-1027_2 (1 pages) PCN-1042_2 (2 pages) PCN-1084_2 (2 pages) PCN-2003-1028_2 (1 pages) PCN-2003-1029_2 (1 pages) pcn0005_1 (1 pages) pcn0404_2 (1 pages) pcn0407_1 (1 pages)
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This data sheet outlines the LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, which is a fully co\ mpliant, customizable single-chip solution. Xilinx DS206 LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, Data Sheet ds206, pci, 32-bit, intiator, target Xilinx, Inc.

This data sheet outlines the LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, which is a fully co\ mpliant, customizable single-chip solution. Xilinx DS206 LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI, Data Sheet ds206, pci, 32-bit, intiator, target Xilinx, Inc.