E-TMP88FW44FG_Customer.book TOSHIBA Semiconductor

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Specifications	E-TMP88FW44FG_Customer.book TOSHIBA Semiconductor
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Page 187 TMP88FW44FG 15.9Status Flag 15.9.1Parity Error When parity determined using the receive data bits differs from the r

Specifications	E-TMP88FW44FG_Customer.book TOSHIBA Semiconductor
Outline	Revision History TMP88FW44FG 1.1 Features 1.2 Pin Assignment 1.4 Pin Names and Functions 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 4.1 SFR 4.2 EBR 4.3 DBR 4. Special Function Register 5. Input/Output Ports 6. Time Base Timer (TBT) and Divider Output (DVO) 7. Watchdog Timer (WDT) 8. 16-Bit TimerCounter 1 (TC1) 9. 16-Bit Timer (CTC) 10. 8-Bit TimerCounter 3 (TC3) 11. 8-Bit TimerCounter 4 (TC4) 12. 8-Bit TimerCounter 5,6(TC5, 6) 13. Motor Control Circuit (PMD: Programmable motor driver) 14. Asynchronous Serial interface (UART1) 15. Asynchronous Serial interface (UART2) 16. Synchronous Serial Interface (SIO) 17. 10-bit AD Converter (ADC) 18. 8-Bit High-speed PWM (HPWM0 and HPWM1) 19. Flash Memory 20. Serial PROM Mode 21. Input/Output Circuitry 22. Electrical Characteristics 23. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/X (LSI).
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Content	Page 187 TMP88FW44FG 15.9Status Flag 15.9.1Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR2<PERR> is set to “1”. The UARTSR2<PERR> is cleared to “0” when the RDBUF2 is read after reading the UARTSR2. Figure 15-5 Generation of Parity Error 15.9.2Framing Error When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR2<FERR> is set to “1”. The UARTSR2<FERR> is cleared to “0” when the RDBUF2 is read after reading the UARTSR2. Figure 15-6 Generation of Framing Error 15.9.3Overrun Error When all bits in the next data are received while unread data are still in RDBUF2, overrun error flag UARTSR2<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF2 are not affected. The UARTSR2<OERR> is cleared to “0” when the RDBUF2 is read after reading the UARTSR2. ParityStop Shift registerpxxxx01pxxxx0xxxx0* RXD pin UARTSR2<PERR> INTRXD interrupt After reading UARTSR2 then RDBUF2 clears PERR. Final bitStop Shift registerxxxx00xxxx0xxx0* RXD pin UARTSR2<FERR> INTRXD interrupt After reading UARTSR2 then RDBUF2 clears FERR.
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