Title Goes Here James Conway JC

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Specifications	Title Goes Here James Conway JC
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Nanoelectronics and More-than-Moore at IMEC Rudi Cartuyvels, Serge Biesemans, Jo De Boeck, Wilfried Vandervorst IMEC, Kapeldr

Specifications	Title Goes Here James Conway JC
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Content	Nanoelectronics and More-than-Moore at IMEC Rudi Cartuyvels, Serge Biesemans, Jo De Boeck, Wilfried Vandervorst IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium ABSTRACT We are entering the 5th decade of CMOS technology scaling. It is slated to bring 22, 16, and 12 nm nodes to production. Geometric scaling will continue using computationally optimized multi patterning 193nm immersion lithography and next generation EUV lithography. For logic devices, the main challenges to be addressed are the transition from planar Si device architectures to FINFET device architectures to better control short channel effects. Engineering the high-k/metal gate and strain engineering solutions introduced in planar device architectures on these 3D topographies will be a non trivial R&D challenge. Overall system energy efficiency is the key challenge to be tackled. Power supply voltage has scaled poorly over the past decade leveling off about 1 Volt. Replacing the Si channel with III-V materials with intrinsic higher channel mobility than the Si channel holds the promise to operate future devices at supply voltages of 0.5 Volt. Tunnel FETS are believed to be a likely candidate to enable scaling beyond the 10 nm node. The TFET architecture potentially enables to combine a steeper sub-threshold slope (<60 mV/decade) with a high on-state current. It will bring us to the 6th decade of nanoelectronic scaling. Innovations developed for logic devices have been further adapted to scale memory technology. High-k dielectrics for MIM capacitors in DRAM, development of vertical FETs access transistors, transition to Cu interconnect enable denser and faster DRAM chips. Floating Body RAM is being researched as next generation DRAM combining switch and memory functions in a single device. Similarly, high-k dielectrics as interpoly and tunnel barriers have enabled floating gate flash technology to continue scaling. Resistive RAM is being researched as next generation NVM technology. 3D TSV technology opens the 3rd dimension for system scaling. It allows to further increase system performance and functionality by enabling new system architectures taking advantage of stacking divergent technologies. Using 3D TSVs, technologies developed for chemical, optical, thermal sensing functionality can be integrated in compact form factors on energy efficient computational engines. Similarly, progress in MEMS and new functional materials will enable various systems innovations to alleviate challenges like efficient health care, sustainable energy consumption and an overall smarter environment. The innovations in nanoelectronics and More-than-Moore technology pose tremendous challenges to physical and chemical analysis. Novel analysis techniques such as AtomProbe (Fig 1) enable to extract high resolution 3D dopant distributions. Defect characterisation of selectively grown III-V layers and characterisation of interface properties of III-V materials with dielectric materials in features sizes relevant for sub 22 nm nodes will be necessary to understand and optimize device operation. FIGURE 1. Elemental analysis (B) with spatial resolution of 0.4 nm in a 40 nm Si FIN using AtomProbe Keywords: CMOS scaling, 3D TSV, MEMS
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