| Specifications | ispLSI 2128VL Data Sheet ispLSI 2128VL Data Sheet ispLSI 2128VL, PLD, ISP, SuperFAST, high density Lattice Semiconductor |
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| Specifications | ispLSI 2128VL Data Sheet ispLSI 2128VL Data Sheet ispLSI 2128VL, PLD, ISP, SuperFAST, high density Lattice Semiconductor |
| Business section |
| Specifications | ispLSI 2128VL Data Sheet ispLSI 2128VL Data Sheet ispLSI 2128VL, PLD, ISP, SuperFAST, high density Lattice Semiconductor |
| Outline | ispLSI 2128VL Data Sheet DC Electrical Characteristics AC Characteristics Signal Configuration: 208 fpBGA Pin Configuration: 176 TQFP Pin Configuration: 160 PQFP Signal Configuration: 100 caBGA Pin Configuration: 100 TQFP Ordering Information |
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| Content | Specifications ispLSI 2128VL 6 Internal Timing Parameters1 Over Recommended Operating Conditions tio 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036/2128VL Inputs UNITS-135-150 MIN. -100 MIN.MAX.MIN.MAX.MAX.DESCRIPTION#2PARAMETER 20Input Buffer Delay—ns tdin21Dedicated Input Delay—ns tgrp22GRP Delay—ns GLB t1ptxor251 Product Term/XOR Path Delay—ns t20ptxor2620 Product Term/XOR Path Delay—ns txoradj27XOR Adjacent Path Delay—ns tgbp28GLB Register Bypass Delay—ns tgsu29GLB Register Setup Time before Clock1.7ns tgh30GLB Register Hold Time after Clock4.8ns tgco31GLB Register Clock to Output Delay—ns 3 tgro32GLB Register Reset to Output Delay—ns tptre33GLB Product Term Reset to Register Delay—ns tptoe34GLB Product Term Output Enable to I/O Cell Delay—ns tptck35GLB Product Term Clock Delay2.8ns ORP tob38Output Buffer Delay—ns tsl39Output Slew Limited Delay Adder—ns GRP t4ptbpc234 Product Term Bypass Path Delay (Combinatorial)—ns t4ptbpr244 Product Term Bypass Path Delay (Registered)—ns torp36ORP Delay—ns torpbp37ORP Bypass Delay—ns Outputs toen40I/O Cell OE to Output Enabled—ns todis41I/O Cell OE to Output Disabled—ns tgoe42Global Output Enable—ns tgy043Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)2.6ns tgy1/244Clock Delay, Y1 or Y2 to Global GLB Clock Line2.8ns Clocks tgr45Global Reset to GLB— 0.9 2.7 1.8 6.2 6.2 6.2 1.0 — — 0.3 4.3 8.9 7.4 4.8 1.6 2.0 5.2 4.7 1.5 0.5 4.9 4.9 4.1 2.6 2.8 7.1 1.0 2.2 1.2 4.2 4.2 4.2 0.5 — — 0.3 1.1 6.6 5.8 4.5 1.6 2.0 3.2 3.2 1.5 0.5 4.0 4.0 3.0 2.1 2.3 4.8 — — — — — — — 1.7 3.3 — — — — 2.1 — — — — — — — — — 2.1 2.3 — 0.4 1.5 1.1 4.0 4.0 4.0 0.0 — — 0.3 0.6 4.9 5.0 4.2 1.6 2.0 2.5 3.0 1.4 0.4 3.5 3.5 2.5 1.7 1.9 3.4 — — — — — — — 1.2 2.8 — — — — 1.2 — — — — — — — — — 1.7 1.9 —ns Global Reset Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm |
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