| Specifications | ispLSI 2128/A Data Sheet ispLSI 2128/A Data Sheet ispLSI, 2128/A, in-system programmable, high density, PLD, lead-free Lattice Semiconductor |
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| Specifications | ispLSI 2128/A Data Sheet ispLSI 2128/A Data Sheet ispLSI, 2128/A, in-system programmable, high density, PLD, lead-free Lattice Semiconductor |
| Business section |
| Specifications | ispLSI 2128/A Data Sheet ispLSI 2128/A Data Sheet ispLSI, 2128/A, in-system programmable, high density, PLD, lead-free Lattice Semiconductor |
| Outline | ispLSI 2128/A Data Sheet DC Electrical Characteristics AC Characteristics Pin Configuration: 160 PQFP Pin Configuration: 176 TQFP Ordering Information Revision History |
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| Content | Specifications ispLSI 2128/A 2 USE ispLSI 2128E FOR NEW DESIGNS Functional Block Diagram Figure 1. ispLSI 2128/A Functional Block Diagram Global Routing Pool (GRP) 0139(10A)/2128 Megablock RESET Input Bus D3D2D1D0D7D6D5D4 Output Routing Pool (ORP)Output Routing Pool (ORP) I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 SDI/IN 7 C7 C6 C5 C4 C3 C2 C1 C0 Output Routing Pool (ORP)Output Routing Pool (ORP) Input Bus IN 5 IN 4 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 95 I/O 94 I/O 93 I/O 92 Output Routing Pool (ORP)Output Routing Pool (ORP) Input Bus CLK 0 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 Y0 Y1 Y2 IN 2 IN 3 B4B5B6B7B0B1B2B3 Output Routing Pool (ORP)Output Routing Pool (ORP) A0 A1 A2 A3 A4 A5 A6 A7 ispEN I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 0 I/O 1 I/O 2 I/O 3 GOE 0 GOE 1 CLK 1 CLK 2 Input Bus SCLK/IN 0 MODE/IN 1 SDO/IN 6 Generic Logic Blocks (GLBs) The device also has 128 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2128 and 2128A device contains four Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2128 and 2128A devices are se- lected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Select devices have been discontinued. See Ordering Information section for product status. |
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| Following Datasheets | 2128v (15 pages) 2128ve (20 pages) 2128vl (17 pages) 21320-R_qhsg (2 pages) 213261_LT3371_Metal_Bonding_Guide_022011_LR451580-1 (64 pages) 21340 (14 pages) 213800_LT6266_ASG_Metalworking_LR395526-1 (16 pages) 213801_LT6267_ASG_Surface_Treat_124_LR658764-1 (32 pages) 213808_01_ASB_2011_Bonding_Section810746-1 (46 pages) 213812_02_ASB_2011_Coatings_Section860919-1 (10 pages) |
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