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Specifications	4.PDF wyoshid1
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L Q2 Q1 V0 + Vin+ –CR Fig. 1. Synchronous Buck Converter Block-Diagram. Depending on the current level required, a sing

Specifications	4.PDF wyoshid1
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Content	L Q2 Q1 V0 + Vin+ –CR Fig. 1. Synchronous Buck Converter Block-Diagram. Depending on the current level required, a single or multiphase buck converter is used. Fig. 1 shows a synchronous buck converter, where Q1 is the control FET and Q2 is the synchronous FET. As shown in Fig. 2, power MOSFETs account for more than half the power loss in a buck converter – an important fact in an application that is critically dependent on efficiency. After further examination, losses can be divided into two FETs, control (Q1) and synchronous (Q2), then calculated using the following approximate equations [3]: P loss Q1 = (Irms2 x RDS(on)) + (I x Qsw/Ig x Vin x f) + (Qg x Vg x f) + (Qoss/2 x Vin x f) … (1) P loss Q1 = (conduction) + (Switching) + (Gate Drive) + (Output capacitance) P loss Q2 = (Irms2 x RDS(on)) + (Qg x Vg x f) + (Qoss/2 x Vin x f) + (Qrr x Vin xf) … (2) P loss Q2 = (conduction) + (Gate Drive) + (Output capacitance) + (Body Diode Reverse Recovery losses) Q1 affects the switching speed, and as such, imposes very critical requirement to minimize the switching charge Qsw and the gate resistance Rg, while maintaining a reasonable on-resistance RDS(on). Ideally, optimum efficiency is best achieved when the switching loss and the conduction loss are approximately the same, giving equal weight to RDS(on) and Qsw. Control FET (Q1) 36% Synchronous FET (Q2) 23% Input Filter 30% Inductor 10%Miscellaneous 1% Control FET (Q1) 36% Synchronous FET (Q2) 23% Input Filter 30% Inductor 10%Miscellaneous 1% Fig. 2. Power Losses Of A Buck Converter; 12VIN, sub-2VOUT 300 kHz The losses in the synchronous FET, Q2 are dominated by conduction losses. Therefore RDS(on) is the most important parameter for the synchronous FET. In practice, the lower the RDS(on) the better the efficiency, but this typically comes with increased cost. However, as the switching frequency approaches 1MHz, we need to keep in mind the power dissipated in the driver [4]. Therefore, low total gate charge Qg of the synchronous FET offers a noticeable advantage. III. SELECTING A MOSFET In order to examine low voltage MOSFET technologies, efficiency measurements were made in a two-phase synchronous buck converter on Intel’s DB850GB, one of the newer commercially available Pentium-4 motherboards [5]. This DC-DC converter design has a 12-volt input and 40 Amp, 1.7-volt output. The buck converter was designed using two D-Pak 30 volt devices in the synchronous FET socket and a single 25V device in a D2Pak in the control FET socket. A number of tests was performed to compare 20V MOSFETs with 30V MOSFETs using the same silicon technology as well as commercially available 30V MOSFETs. Specifications for the MOSFETs are shown in Table I.
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