| Specifications | ispLSI 2096/A Data Sheet ispLSI 2096/A Data Sheet ispLSI, 2096/A, in-system programmable, high density, lead-free Lattice Semiconductor |
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| Specifications | ispLSI 2096/A Data Sheet ispLSI 2096/A Data Sheet ispLSI, 2096/A, in-system programmable, high density, lead-free Lattice Semiconductor |
| Business section |
| Specifications | ispLSI 2096/A Data Sheet ispLSI 2096/A Data Sheet ispLSI, 2096/A, in-system programmable, high density, lead-free Lattice Semiconductor |
| Outline | ispLSI 2096/A Data Sheet DC Electrical Characteristics AC Characteristics Pin Configuration: 128 PQFP/TQFP Ordering Information Revision History |
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| Content | Specifications ispLSI 2096/A 2 USE ispLSI 2096E FOR NEW DESIGNS Functional Block Diagram Figure 1. ispLSI 2096/A Functional Block Diagram The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2096 and 2096A device contains three Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2096 and 2096A devices are se- lected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. A0 A3 A1 A2 B7 B4 B6 B5 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus Global Routing Pool (GRP) CLK 0 CLK 1 CLK 2 I/O 95 I/O 94 I/O 93 I/O 92 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 IN 2 SCLK/IN 3 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 Y0 Y1 Y2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 SDI/IN 0 MODE/IN 1 SDO RESET ispEN GOE 1 GOE 0 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 Input Bus 0917 Megablock C7C6C5C4 A4A5A6A7 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus B0B1B2B3 Output Routing Pool (ORP) C3C2C1C0 Output Routing Pool (ORP) Input Bus I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 IN 5 IN 4 Generic Logic Blocks (GLBs) Select devices have been discontinued. See Ordering Information section for product status. |
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| Following Datasheets | 2096v (11 pages) 2096ve (13 pages) 2096vl (11 pages) 209ce598-b279-4102-bb88-e7cefa29b57e (1 pages) 20ac79ba-16f5-4853-948f-f71c563c5232 (2 pages) 20clq045 (4 pages) 20G_SY-PQG208 (1 pages) 20GC001_1 (40 pages) 20GC004_1_1 (24 pages) 20GC014_Revb-1_1 (32 pages) |
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